210 lines
7.3 KiB
C
210 lines
7.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2022 Intel Corporation
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*/
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#ifndef _VRB_PMD_H_
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#define _VRB_PMD_H_
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#include "acc_common.h"
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#include "vrb1_pf_enum.h"
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#include "vrb1_vf_enum.h"
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#include "vrb_cfg.h"
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/* Helper macro for logging */
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#define rte_bbdev_log(level, fmt, ...) \
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rte_log(RTE_LOG_ ## level, vrb_logtype, fmt "\n", \
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##__VA_ARGS__)
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#ifdef RTE_LIBRTE_BBDEV_DEBUG
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#define rte_bbdev_log_debug(fmt, ...) \
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rte_bbdev_log(DEBUG, "vrb_pmd: " fmt, \
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##__VA_ARGS__)
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#else
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#define rte_bbdev_log_debug(fmt, ...)
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#endif
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/* VRB1 PF and VF driver names */
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#define VRB_PF_DRIVER_NAME intel_vran_boost_pf
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#define VRB_VF_DRIVER_NAME intel_vran_boost_vf
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/* VRB1 PCI vendor & device IDs */
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#define RTE_VRB1_VENDOR_ID (0x8086)
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#define RTE_VRB1_PF_DEVICE_ID (0x57C0)
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#define RTE_VRB1_VF_DEVICE_ID (0x57C1)
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#define VRB1_VARIANT 2
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#define VRB_NUM_ACCS 6
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#define VRB_MAX_QGRPS 32
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#define VRB_MAX_AQS 32
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#define ACC_STATUS_WAIT 10
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#define ACC_STATUS_TO 100
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/* VRB1 specific flags */
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#define VRB1_NUM_VFS 16
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#define VRB1_NUM_QGRPS 16
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#define VRB1_NUM_AQS 16
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#define VRB1_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */
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#define VRB1_VF_ID_SHIFT 4 /* Queue Index Hierarchy */
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#define VRB1_WORDS_IN_ARAM_SIZE (256 * 1024 / 4)
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/* VRB1 Mapping of signals for the available engines */
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#define VRB1_SIG_UL_5G 0
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#define VRB1_SIG_UL_5G_LAST 4
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#define VRB1_SIG_DL_5G 10
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#define VRB1_SIG_DL_5G_LAST 11
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#define VRB1_SIG_UL_4G 12
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#define VRB1_SIG_UL_4G_LAST 16
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#define VRB1_SIG_DL_4G 21
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#define VRB1_SIG_DL_4G_LAST 23
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#define VRB1_SIG_FFT 24
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#define VRB1_SIG_FFT_LAST 24
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#define VRB1_NUM_ACCS 5
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/* VRB1 Configuration */
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#define VRB1_FABRIC_MODE 0x8000103
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#define VRB1_CFG_DMA_ERROR 0x3DF
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#define VRB1_CFG_AXI_CACHE 0x11
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#define VRB1_CFG_QMGR_HI_P 0x0F0F
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#define VRB1_RESET_HARD 0x1FF
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#define VRB1_ENGINES_MAX 9
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#define VRB1_GPEX_AXIMAP_NUM 17
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#define VRB1_CLOCK_GATING_EN 0x30000
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#define VRB1_FFT_CFG_0 0x2001
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#define VRB1_FFT_RAM_EN 0x80008000
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#define VRB1_FFT_RAM_DIS 0x0
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#define VRB1_FFT_RAM_SIZE 512
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#define VRB1_CLK_EN 0x00010A01
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#define VRB1_CLK_DIS 0x01F10A01
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#define VRB1_PG_MASK_0 0x1F
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#define VRB1_PG_MASK_1 0xF
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#define VRB1_PG_MASK_2 0x1
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#define VRB1_PG_MASK_3 0x0
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#define VRB1_PG_MASK_FFT 1
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#define VRB1_PG_MASK_4GUL 4
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#define VRB1_PG_MASK_5GUL 8
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#define VRB1_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */
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#define VRB1_MAX_PF_MSIX (256+32)
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#define VRB1_MAX_VF_MSIX (256+7)
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struct acc_registry_addr {
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unsigned int dma_ring_dl5g_hi;
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unsigned int dma_ring_dl5g_lo;
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unsigned int dma_ring_ul5g_hi;
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unsigned int dma_ring_ul5g_lo;
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unsigned int dma_ring_dl4g_hi;
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unsigned int dma_ring_dl4g_lo;
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unsigned int dma_ring_ul4g_hi;
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unsigned int dma_ring_ul4g_lo;
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unsigned int dma_ring_fft_hi;
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unsigned int dma_ring_fft_lo;
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unsigned int ring_size;
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unsigned int info_ring_hi;
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unsigned int info_ring_lo;
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unsigned int info_ring_en;
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unsigned int info_ring_ptr;
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unsigned int tail_ptrs_dl5g_hi;
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unsigned int tail_ptrs_dl5g_lo;
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unsigned int tail_ptrs_ul5g_hi;
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unsigned int tail_ptrs_ul5g_lo;
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unsigned int tail_ptrs_dl4g_hi;
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unsigned int tail_ptrs_dl4g_lo;
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unsigned int tail_ptrs_ul4g_hi;
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unsigned int tail_ptrs_ul4g_lo;
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unsigned int tail_ptrs_fft_hi;
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unsigned int tail_ptrs_fft_lo;
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unsigned int depth_log0_offset;
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unsigned int depth_log1_offset;
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unsigned int qman_group_func;
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unsigned int hi_mode;
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unsigned int pf_mode;
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unsigned int pmon_ctrl_a;
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unsigned int pmon_ctrl_b;
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unsigned int pmon_ctrl_c;
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unsigned int vf2pf_doorbell;
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unsigned int pf2vf_doorbell;
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};
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/* Structure holding registry addresses for PF */
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static const struct acc_registry_addr vrb1_pf_reg_addr = {
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.dma_ring_dl5g_hi = VRB1_PfDmaFec5GdlDescBaseHiRegVf,
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.dma_ring_dl5g_lo = VRB1_PfDmaFec5GdlDescBaseLoRegVf,
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.dma_ring_ul5g_hi = VRB1_PfDmaFec5GulDescBaseHiRegVf,
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.dma_ring_ul5g_lo = VRB1_PfDmaFec5GulDescBaseLoRegVf,
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.dma_ring_dl4g_hi = VRB1_PfDmaFec4GdlDescBaseHiRegVf,
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.dma_ring_dl4g_lo = VRB1_PfDmaFec4GdlDescBaseLoRegVf,
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.dma_ring_ul4g_hi = VRB1_PfDmaFec4GulDescBaseHiRegVf,
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.dma_ring_ul4g_lo = VRB1_PfDmaFec4GulDescBaseLoRegVf,
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.dma_ring_fft_hi = VRB1_PfDmaFftDescBaseHiRegVf,
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.dma_ring_fft_lo = VRB1_PfDmaFftDescBaseLoRegVf,
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.ring_size = VRB1_PfQmgrRingSizeVf,
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.info_ring_hi = VRB1_PfHiInfoRingBaseHiRegPf,
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.info_ring_lo = VRB1_PfHiInfoRingBaseLoRegPf,
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.info_ring_en = VRB1_PfHiInfoRingIntWrEnRegPf,
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.info_ring_ptr = VRB1_PfHiInfoRingPointerRegPf,
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.tail_ptrs_dl5g_hi = VRB1_PfDmaFec5GdlRespPtrHiRegVf,
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.tail_ptrs_dl5g_lo = VRB1_PfDmaFec5GdlRespPtrLoRegVf,
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.tail_ptrs_ul5g_hi = VRB1_PfDmaFec5GulRespPtrHiRegVf,
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.tail_ptrs_ul5g_lo = VRB1_PfDmaFec5GulRespPtrLoRegVf,
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.tail_ptrs_dl4g_hi = VRB1_PfDmaFec4GdlRespPtrHiRegVf,
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.tail_ptrs_dl4g_lo = VRB1_PfDmaFec4GdlRespPtrLoRegVf,
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.tail_ptrs_ul4g_hi = VRB1_PfDmaFec4GulRespPtrHiRegVf,
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.tail_ptrs_ul4g_lo = VRB1_PfDmaFec4GulRespPtrLoRegVf,
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.tail_ptrs_fft_hi = VRB1_PfDmaFftRespPtrHiRegVf,
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.tail_ptrs_fft_lo = VRB1_PfDmaFftRespPtrLoRegVf,
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.depth_log0_offset = VRB1_PfQmgrGrpDepthLog20Vf,
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.depth_log1_offset = VRB1_PfQmgrGrpDepthLog21Vf,
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.qman_group_func = VRB1_PfQmgrGrpFunction0,
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.hi_mode = VRB1_PfHiMsixVectorMapperPf,
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.pf_mode = VRB1_PfHiPfMode,
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.pmon_ctrl_a = VRB1_PfPermonACntrlRegVf,
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.pmon_ctrl_b = VRB1_PfPermonBCntrlRegVf,
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.pmon_ctrl_c = VRB1_PfPermonCCntrlRegVf,
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.vf2pf_doorbell = 0,
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.pf2vf_doorbell = 0,
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};
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/* Structure holding registry addresses for VF */
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static const struct acc_registry_addr vrb1_vf_reg_addr = {
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.dma_ring_dl5g_hi = VRB1_VfDmaFec5GdlDescBaseHiRegVf,
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.dma_ring_dl5g_lo = VRB1_VfDmaFec5GdlDescBaseLoRegVf,
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.dma_ring_ul5g_hi = VRB1_VfDmaFec5GulDescBaseHiRegVf,
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.dma_ring_ul5g_lo = VRB1_VfDmaFec5GulDescBaseLoRegVf,
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.dma_ring_dl4g_hi = VRB1_VfDmaFec4GdlDescBaseHiRegVf,
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.dma_ring_dl4g_lo = VRB1_VfDmaFec4GdlDescBaseLoRegVf,
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.dma_ring_ul4g_hi = VRB1_VfDmaFec4GulDescBaseHiRegVf,
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.dma_ring_ul4g_lo = VRB1_VfDmaFec4GulDescBaseLoRegVf,
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.dma_ring_fft_hi = VRB1_VfDmaFftDescBaseHiRegVf,
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.dma_ring_fft_lo = VRB1_VfDmaFftDescBaseLoRegVf,
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.ring_size = VRB1_VfQmgrRingSizeVf,
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.info_ring_hi = VRB1_VfHiInfoRingBaseHiVf,
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.info_ring_lo = VRB1_VfHiInfoRingBaseLoVf,
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.info_ring_en = VRB1_VfHiInfoRingIntWrEnVf,
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.info_ring_ptr = VRB1_VfHiInfoRingPointerVf,
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.tail_ptrs_dl5g_hi = VRB1_VfDmaFec5GdlRespPtrHiRegVf,
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.tail_ptrs_dl5g_lo = VRB1_VfDmaFec5GdlRespPtrLoRegVf,
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.tail_ptrs_ul5g_hi = VRB1_VfDmaFec5GulRespPtrHiRegVf,
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.tail_ptrs_ul5g_lo = VRB1_VfDmaFec5GulRespPtrLoRegVf,
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.tail_ptrs_dl4g_hi = VRB1_VfDmaFec4GdlRespPtrHiRegVf,
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.tail_ptrs_dl4g_lo = VRB1_VfDmaFec4GdlRespPtrLoRegVf,
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.tail_ptrs_ul4g_hi = VRB1_VfDmaFec4GulRespPtrHiRegVf,
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.tail_ptrs_ul4g_lo = VRB1_VfDmaFec4GulRespPtrLoRegVf,
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.tail_ptrs_fft_hi = VRB1_VfDmaFftRespPtrHiRegVf,
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.tail_ptrs_fft_lo = VRB1_VfDmaFftRespPtrLoRegVf,
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.depth_log0_offset = VRB1_VfQmgrGrpDepthLog20Vf,
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.depth_log1_offset = VRB1_VfQmgrGrpDepthLog21Vf,
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.qman_group_func = VRB1_VfQmgrGrpFunction0Vf,
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.hi_mode = VRB1_VfHiMsixVectorMapperVf,
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.pf_mode = 0,
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.pmon_ctrl_a = VRB1_VfPmACntrlRegVf,
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.pmon_ctrl_b = VRB1_VfPmBCntrlRegVf,
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.pmon_ctrl_c = VRB1_VfPmCCntrlRegVf,
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.vf2pf_doorbell = VRB1_VfHiVfToPfDbellVf,
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.pf2vf_doorbell = VRB1_VfHiPfToVfDbellVf,
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};
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#endif /* _VRB_PMD_H_ */
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