/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright (c) 2016 - 2018 Cavium Inc.
 * All rights reserved.
 * www.cavium.com
 */

#define  CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
	0

#define  CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE		( \
		0xfffUL << 0)

#define  CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
	12

#define  CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE		( \
		0xfffUL << 12)

#define  CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
	24

#define  CDU_REG_CID_ADDR_PARAMS_NCIB			( \
		0xffUL << 24) /* @DPDK */

#define  XSDM_REG_OPERATION_GEN \
	0xf80408UL
#define  NIG_REG_RX_BRB_OUT_EN \
	0x500e18UL
#define  NIG_REG_STORM_OUT_EN \
	0x500e08UL
#define  PSWRQ2_REG_L2P_VALIDATE_VFID \
	0x240c50UL
#define  PGLUE_B_REG_USE_CLIENTID_IN_TAG	\
	0x2aae04UL
#define  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER	\
	0x2aa16cUL
#define  BAR0_MAP_REG_MSDM_RAM \
	0x1d00000UL
#define  BAR0_MAP_REG_USDM_RAM \
	0x1d80000UL
#define  BAR0_MAP_REG_PSDM_RAM \
	0x1f00000UL
#define  BAR0_MAP_REG_TSDM_RAM \
	0x1c80000UL
#define  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
	0x5011f4UL
#define  PRS_REG_SEARCH_TCP \
	0x1f0400UL
#define  PRS_REG_SEARCH_UDP \
	0x1f0404UL
#define  PRS_REG_SEARCH_OPENFLOW	\
	0x1f0434UL
#define  TM_REG_PF_ENABLE_CONN \
	0x2c043cUL
#define  TM_REG_PF_ENABLE_TASK \
	0x2c0444UL
#define  TM_REG_PF_SCAN_ACTIVE_CONN \
	0x2c04fcUL
#define  TM_REG_PF_SCAN_ACTIVE_TASK \
	0x2c0500UL
#define  IGU_REG_LEADING_EDGE_LATCH \
	0x18082cUL
#define  IGU_REG_TRAILING_EDGE_LATCH \
	0x180830UL
#define  QM_REG_USG_CNT_PF_TX \
	0x2f2eacUL
#define  QM_REG_USG_CNT_PF_OTHER	\
	0x2f2eb0UL
#define  DORQ_REG_PF_DB_ENABLE \
	0x100508UL
#define  QM_REG_PF_EN \
	0x2f2ea4UL
#define  TCFC_REG_STRONG_ENABLE_PF \
	0x2d0708UL
#define  CCFC_REG_STRONG_ENABLE_PF \
	0x2e0708UL
#define  PGLUE_B_REG_PGL_ADDR_88_F0 \
	0x2aa404UL
#define  PGLUE_B_REG_PGL_ADDR_8C_F0 \
	0x2aa408UL
#define  PGLUE_B_REG_PGL_ADDR_90_F0 \
	0x2aa40cUL
#define  PGLUE_B_REG_PGL_ADDR_94_F0 \
	0x2aa410UL
#define  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
	0x2aa138UL
#define  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
	0x2aa174UL
#define  MISC_REG_GEN_PURP_CR0 \
	0x008c80UL
#define  MCP_REG_SCRATCH	\
	0xe20000UL
#define  CNIG_REG_NW_PORT_MODE_BB_B0 \
	0x218200UL
#define  MISCS_REG_CHIP_NUM \
	0x00976cUL
#define  MISCS_REG_CHIP_REV \
	0x009770UL
#define  MISCS_REG_CMT_ENABLED_FOR_PAIR \
	0x00971cUL
#define  MISCS_REG_CHIP_TEST_REG	\
	0x009778UL
#define  MISCS_REG_CHIP_METAL \
	0x009774UL
#define  BRB_REG_HEADER_SIZE \
	0x340804UL
#define  BTB_REG_HEADER_SIZE \
	0xdb0804UL
#define  CAU_REG_LONG_TIMEOUT_THRESHOLD \
	0x1c0708UL
#define  CCFC_REG_ACTIVITY_COUNTER \
	0x2e8800UL
#define  CDU_REG_CID_ADDR_PARAMS	\
	0x580900UL
#define  DBG_REG_CLIENT_ENABLE \
	0x010004UL
#define  DMAE_REG_INIT \
	0x00c000UL
#define  DORQ_REG_IFEN \
	0x100040UL
#define  GRC_REG_TIMEOUT_EN \
	0x050404UL
#define  IGU_REG_BLOCK_CONFIGURATION \
	0x180040UL
#define  MCM_REG_INIT \
	0x1200000UL
#define  MCP2_REG_DBG_DWORD_ENABLE \
	0x052404UL
#define  MISC_REG_PORT_MODE \
	0x008c00UL
#define MISC_REG_BLOCK_256B_EN \
	0x008c14UL
#define MISCS_REG_RESET_PL_HV \
	0x009060UL
#define  MISCS_REG_CLK_100G_MODE	\
	0x009070UL
#define MISCS_REG_RESET_PL_HV_2_K2 \
	0x009150UL
#define  MSDM_REG_ENABLE_IN1 \
	0xfc0004UL
#define  MSEM_REG_ENABLE_IN \
	0x1800004UL
#define  NIG_REG_CM_HDR \
	0x500840UL
#define  NCSI_REG_CONFIG	\
	0x040200UL
#define PSWRQ2_REG_RBC_DONE \
	0x240000UL
#define PSWRQ2_REG_CFG_DONE \
	0x240004UL
#define  PBF_REG_INIT \
	0xd80000UL
#define  PTU_REG_ATC_INIT_ARRAY \
	0x560000UL
#define  PCM_REG_INIT \
	0x1100000UL
#define  PGLUE_B_REG_ADMIN_PER_PF_REGION	\
	0x2a9000UL
#define  PRM_REG_DISABLE_PRM \
	0x230000UL
#define  PRS_REG_SOFT_RST \
	0x1f0000UL
#define  PSDM_REG_ENABLE_IN1 \
	0xfa0004UL
#define  PSEM_REG_ENABLE_IN \
	0x1600004UL
#define  PSWRQ_REG_DBG_SELECT \
	0x280020UL
#define  PSWRQ2_REG_CDUT_P_SIZE \
	0x24000cUL
#define  PSWHST_REG_DISCARD_INTERNAL_WRITES \
	0x2a0040UL
#define  PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
	0x29e050UL
#define  PSWRD_REG_DBG_SELECT \
	0x29c040UL
#define  PSWRD2_REG_CONF11 \
	0x29d064UL
#define  PSWWR_REG_USDM_FULL_TH \
	0x29a040UL
#define  PSWWR2_REG_CDU_FULL_TH2	\
	0x29b040UL
#define  QM_REG_MAXPQSIZE_0 \
	0x2f0434UL
#define  RSS_REG_RSS_INIT_EN \
	0x238804UL
#define  RDIF_REG_STOP_ON_ERROR \
	0x300040UL
#define  SRC_REG_SOFT_RST \
	0x23874cUL
#define  TCFC_REG_ACTIVITY_COUNTER \
	0x2d8800UL
#define  TCM_REG_INIT \
	0x1180000UL
#define  TM_REG_PXP_READ_DATA_FIFO_INIT \
	0x2c0014UL
#define  TSDM_REG_ENABLE_IN1 \
	0xfb0004UL
#define  TSEM_REG_ENABLE_IN \
	0x1700004UL
#define  TDIF_REG_STOP_ON_ERROR \
	0x310040UL
#define  UCM_REG_INIT \
	0x1280000UL
#define  UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
	0x051004UL
#define  USDM_REG_ENABLE_IN1 \
	0xfd0004UL
#define  USEM_REG_ENABLE_IN \
	0x1900004UL
#define  XCM_REG_INIT \
	0x1000000UL
#define  XSDM_REG_ENABLE_IN1 \
	0xf80004UL
#define  XSEM_REG_ENABLE_IN \
	0x1400004UL
#define  YCM_REG_INIT \
	0x1080000UL
#define  YSDM_REG_ENABLE_IN1 \
	0xf90004UL
#define  YSEM_REG_ENABLE_IN \
	0x1500004UL
#define  XYLD_REG_SCBD_STRICT_PRIO \
	0x4c0000UL
#define  TMLD_REG_SCBD_STRICT_PRIO \
	0x4d0000UL
#define  MULD_REG_SCBD_STRICT_PRIO \
	0x4e0000UL
#define  YULD_REG_SCBD_STRICT_PRIO \
	0x4c8000UL
#define  MISC_REG_SHARED_MEM_ADDR \
	0x008c20UL
#define  DMAE_REG_GO_C0 \
	0x00c048UL
#define  DMAE_REG_GO_C1 \
	0x00c04cUL
#define  DMAE_REG_GO_C2 \
	0x00c050UL
#define  DMAE_REG_GO_C3 \
	0x00c054UL
#define  DMAE_REG_GO_C4 \
	0x00c058UL
#define  DMAE_REG_GO_C5 \
	0x00c05cUL
#define  DMAE_REG_GO_C6 \
	0x00c060UL
#define  DMAE_REG_GO_C7 \
	0x00c064UL
#define  DMAE_REG_GO_C8 \
	0x00c068UL
#define  DMAE_REG_GO_C9 \
	0x00c06cUL
#define  DMAE_REG_GO_C10	\
	0x00c070UL
#define  DMAE_REG_GO_C11	\
	0x00c074UL
#define  DMAE_REG_GO_C12	\
	0x00c078UL
#define  DMAE_REG_GO_C13	\
	0x00c07cUL
#define  DMAE_REG_GO_C14	\
	0x00c080UL
#define  DMAE_REG_GO_C15	\
	0x00c084UL
#define  DMAE_REG_GO_C16	\
	0x00c088UL
#define  DMAE_REG_GO_C17	\
	0x00c08cUL
#define  DMAE_REG_GO_C18	\
	0x00c090UL
#define  DMAE_REG_GO_C19	\
	0x00c094UL
#define  DMAE_REG_GO_C20	\
	0x00c098UL
#define  DMAE_REG_GO_C21	\
	0x00c09cUL
#define  DMAE_REG_GO_C22	\
	0x00c0a0UL
#define  DMAE_REG_GO_C23	\
	0x00c0a4UL
#define  DMAE_REG_GO_C24	\
	0x00c0a8UL
#define  DMAE_REG_GO_C25	\
	0x00c0acUL
#define  DMAE_REG_GO_C26	\
	0x00c0b0UL
#define  DMAE_REG_GO_C27	\
	0x00c0b4UL
#define  DMAE_REG_GO_C28	\
	0x00c0b8UL
#define  DMAE_REG_GO_C29	\
	0x00c0bcUL
#define  DMAE_REG_GO_C30	\
	0x00c0c0UL
#define  DMAE_REG_GO_C31	\
	0x00c0c4UL
#define  DMAE_REG_CMD_MEM \
	0x00c800UL
#define  QM_REG_MAXPQSIZETXSEL_0	\
	0x2f0440UL
#define  QM_REG_SDMCMDREADY \
	0x2f1e10UL
#define  QM_REG_SDMCMDADDR \
	0x2f1e04UL
#define  QM_REG_SDMCMDDATALSB \
	0x2f1e08UL
#define  QM_REG_SDMCMDDATAMSB \
	0x2f1e0cUL
#define  QM_REG_SDMCMDGO	\
	0x2f1e14UL
#define  QM_REG_RLPFCRD \
	0x2f4d80UL
#define  QM_REG_RLPFINCVAL \
	0x2f4c80UL
#define  QM_REG_RLGLBLCRD \
	0x2f4400UL
#define  QM_REG_RLGLBLINCVAL \
	0x2f3400UL
#define  IGU_REG_ATTENTION_ENABLE \
	0x18083cUL
#define  IGU_REG_ATTN_MSG_ADDR_L	\
	0x180820UL
#define  IGU_REG_ATTN_MSG_ADDR_H	\
	0x180824UL
#define IGU_REG_LEADING_EDGE_LATCH \
	0x18082cUL
#define IGU_REG_TRAILING_EDGE_LATCH \
	0x180830UL
#define IGU_REG_ATTENTION_ACK_BITS \
	0x180838UL
#define IGU_REG_PBA_STS_PF \
	0x180d20UL
#define IGU_REG_PF_FUNCTIONAL_CLEANUP \
	0x181210UL
#define IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED \
	0x18042cUL
#define IGU_REG_PBA_STS_PF_SIZE 5
#define IGU_REG_PBA_STS_PF \
	0x180d20UL
#define  MISC_REG_AEU_GENERAL_ATTN_0 \
	0x008400UL
#define  CAU_REG_SB_ADDR_MEMORY \
	0x1c8000UL
#define  CAU_REG_SB_VAR_MEMORY \
	0x1c6000UL
#define  CAU_REG_PI_MEMORY \
	0x1d0000UL
#define  IGU_REG_PF_CONFIGURATION \
	0x180800UL
#define  MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
	0x00849cUL
#define  MISC_REG_AEU_MASK_ATTN_IGU \
	0x008494UL
#define  IGU_REG_CLEANUP_STATUS_0 \
	0x180980UL
#define  IGU_REG_CLEANUP_STATUS_1 \
	0x180a00UL
#define  IGU_REG_CLEANUP_STATUS_2 \
	0x180a80UL
#define  IGU_REG_CLEANUP_STATUS_3 \
	0x180b00UL
#define  IGU_REG_CLEANUP_STATUS_4 \
	0x180b80UL
#define  IGU_REG_COMMAND_REG_32LSB_DATA \
	0x180840UL
#define  IGU_REG_COMMAND_REG_CTRL \
	0x180848UL
#define  IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN	( \
		0x1UL << 1)
#define  IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN	( \
		0x1UL << 0)
#define  IGU_REG_MAPPING_MEMORY \
	0x184000UL
#define  MISCS_REG_GENERIC_POR_0	\
	0x0096d4UL
#define  MCP_REG_NVM_CFG4 \
	0xe0642cUL
#define  MCP_REG_NVM_CFG4_FLASH_SIZE	( \
		0x7UL << 0)
#define  MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
	0
#define CCFC_REG_STRONG_ENABLE_VF 0x2e070cUL
#define CNIG_REG_PMEG_IF_CMD_BB_B0 0x21821cUL
#define CNIG_REG_PMEG_IF_ADDR_BB_B0 0x218224UL
#define CNIG_REG_PMEG_IF_WRDATA_BB_B0 0x218228UL
#define NWM_REG_MAC0 0x800400UL
#define NWM_REG_MAC0_SIZE 256
#define CNIG_REG_NIG_PORT0_CONF_K2 0x218200UL
#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT 0
#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT 1
#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT 3
#define ETH_MAC_REG_XIF_MODE 0x000080UL
#define ETH_MAC_REG_XIF_MODE_XGMII_SHIFT 0
#define ETH_MAC_REG_FRM_LENGTH 0x000014UL
#define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT 0
#define ETH_MAC_REG_TX_IPG_LENGTH 0x000044UL
#define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT 0
#define ETH_MAC_REG_RX_FIFO_SECTIONS 0x00001cUL
#define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT 0
#define ETH_MAC_REG_TX_FIFO_SECTIONS 0x000020UL
#define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT 16
#define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT 0
#define ETH_MAC_REG_COMMAND_CONFIG 0x000008UL
#define MISC_REG_RESET_PL_PDA_VAUX 0x008090UL
#define MISC_REG_XMAC_CORE_PORT_MODE 0x008c08UL
#define MISC_REG_XMAC_PHY_PORT_MODE 0x008c04UL
#define XMAC_REG_MODE 0x210008UL
#define XMAC_REG_RX_MAX_SIZE 0x210040UL
#define XMAC_REG_TX_CTRL_LO 0x210020UL
#define XMAC_REG_CTRL 0x210000UL
#define XMAC_REG_RX_CTRL 0x210030UL
#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE (0x1UL << 12)
#define MISC_REG_CLK_100G_MODE 0x008c10UL
#define MISC_REG_OPTE_MODE 0x008c0cUL
#define NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH 0x501b84UL
#define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL
#define PRS_REG_SEARCH_TAG1 0x1f0444UL
#define PRS_REG_SEARCH_TCP_FIRST_FRAG 0x1f0410UL
#define MISCS_REG_PLL_MAIN_CTRL_4 0x00974cUL
#define MISCS_REG_ECO_RESERVED 0x0097b4UL
#define PGLUE_B_REG_PF_BAR0_SIZE 0x2aae60UL
#define PGLUE_B_REG_PF_BAR1_SIZE 0x2aae64UL
#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL
#define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE 0x501b00UL
#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL
#define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL
#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL
#define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL
#define NIG_REG_LLH_FUNC_FILTER_MODE 0x501ac0UL
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE 0x501b00UL
#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL
#define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL
#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL
#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL
#define XMAC_REG_CTRL_TX_EN (0x1UL << 0)
#define XMAC_REG_CTRL_RX_EN (0x1UL << 1)
#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE (0xffUL << 24) /* @DPDK */
#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE (0xffUL << 16)
#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT 16
#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE (0xffUL << 16)
#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE (0xffUL << 24) /* @DPDK */
#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK (0xfffUL << 0)
#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT 0
#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK (0xfffUL << 0)
#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT 0
#define PSWRQ2_REG_ILT_MEMORY 0x260000UL
#define QM_REG_WFQPFWEIGHT 0x2f4e80UL
#define QM_REG_WFQVPWEIGHT 0x2fa000UL
#define NIG_REG_LB_ARB_CREDIT_WEIGHT_0 0x50160cUL
#define NIG_REG_TX_ARB_CREDIT_WEIGHT_0 0x501f88UL
#define NIG_REG_LB_ARB_CREDIT_WEIGHT_1 0x501610UL
#define NIG_REG_TX_ARB_CREDIT_WEIGHT_1 0x501f8cUL
#define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_0 0x5015e4UL
#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0 0x501f58UL
#define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_1 0x5015e8UL
#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_1 0x501f5cUL
#define NIG_REG_LB_ARB_CLIENT_IS_STRICT 0x5015c0UL
#define NIG_REG_TX_ARB_CLIENT_IS_STRICT 0x501f34UL
#define NIG_REG_LB_ARB_CLIENT_IS_SUBJECT2WFQ 0x5015c4UL
#define NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x501f38UL
#define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_BASE_TYPE_SHIFT 1
#define NIG_REG_TX_LB_GLBRATELIMIT_CTRL 0x501f1cUL
#define NIG_REG_TX_LB_GLBRATELIMIT_INC_PERIOD 0x501f20UL
#define NIG_REG_TX_LB_GLBRATELIMIT_INC_VALUE 0x501f24UL
#define NIG_REG_TX_LB_GLBRATELIMIT_MAX_VALUE 0x501f28UL
#define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_EN_SHIFT 0
#define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_BASE_TYPE_SHIFT 1
#define NIG_REG_LB_BRBRATELIMIT_CTRL 0x50150cUL
#define NIG_REG_LB_BRBRATELIMIT_INC_PERIOD 0x501510UL
#define NIG_REG_LB_BRBRATELIMIT_INC_VALUE 0x501514UL
#define NIG_REG_LB_BRBRATELIMIT_MAX_VALUE 0x501518UL
#define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_EN_SHIFT 0
#define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_BASE_TYPE_0_SHIFT 1
#define NIG_REG_LB_TCRATELIMIT_CTRL_0 0x501520UL
#define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0 0x501540UL
#define NIG_REG_LB_TCRATELIMIT_INC_VALUE_0 0x501560UL
#define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_0 0x501580UL
#define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_EN_0_SHIFT 0
#define NIG_REG_PRIORITY_FOR_TC_0 0x501bccUL
#define NIG_REG_RX_TC0_PRIORITY_MASK 0x501becUL
#define PRS_REG_ETS_ARB_CREDIT_WEIGHT_1 0x1f0540UL
#define PRS_REG_ETS_ARB_CREDIT_WEIGHT_0 0x1f0534UL
#define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_1 0x1f053cUL
#define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_0 0x1f0530UL
#define PRS_REG_ETS_ARB_CLIENT_IS_STRICT 0x1f0514UL
#define PRS_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ 0x1f0518UL
#define BRB_REG_TOTAL_MAC_SIZE 0x3408c0UL
#define BRB_REG_SHARED_HR_AREA 0x340880UL
#define BRB_REG_TC_GUARANTIED_0 0x340900UL
#define BRB_REG_MAIN_TC_GUARANTIED_HYST_0 0x340978UL
#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_0 0x340c60UL
#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_0 0x340d38UL
#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_0 0x340ab0UL
#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_0 0x340b88UL
#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_0 0x340c00UL
#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_0 0x340cd8UL
#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_0 0x340a50UL
#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_0 0x340b28UL
#define PRS_REG_VXLAN_PORT 0x1f0738UL
#define NIG_REG_VXLAN_PORT 0x50105cUL
#define PBF_REG_VXLAN_PORT 0xd80518UL
#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
#define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
#define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2
#define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
#define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0
#define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1
#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
#define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
#define PRS_REG_NGE_PORT 0x1f086cUL
#define NIG_REG_NGE_PORT 0x508b38UL
#define PBF_REG_NGE_PORT 0xd8051cUL
#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
#define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL
#define NIG_REG_NGE_IP_ENABLE 0x508b28UL
#define NIG_REG_NGE_COMP_VER 0x508b30UL
#define PBF_REG_NGE_COMP_VER 0xd80524UL
#define PRS_REG_NGE_COMP_VER 0x1f0878UL
#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL
#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL
#define NIG_REG_PKT_PRIORITY_TO_TC 0x501ba4UL
#define PGLUE_B_REG_START_INIT_PTT_GTT 0x2a8008UL
#define PGLUE_B_REG_INIT_DONE_PTT_GTT 0x2a800cUL
#define MISC_REG_AEU_GENERAL_ATTN_35 0x00848cUL
#define MCP_REG_CPU_STATE 0xe05004UL
#define MCP_REG_CPU_MODE 0xe05000UL
#define MCP_REG_CPU_MODE_SOFT_HALT (0x1UL << 10)
#define MCP_REG_CPU_EVENT_MASK 0xe05008UL
#define PSWHST_REG_VF_DISABLED_ERROR_VALID 0x2a0060UL
#define PSWHST_REG_VF_DISABLED_ERROR_ADDRESS 0x2a0064UL
#define PSWHST_REG_VF_DISABLED_ERROR_DATA 0x2a005cUL
#define PSWHST_REG_INCORRECT_ACCESS_VALID 0x2a0070UL
#define PSWHST_REG_INCORRECT_ACCESS_ADDRESS 0x2a0074UL
#define PSWHST_REG_INCORRECT_ACCESS_DATA 0x2a0068UL
#define PSWHST_REG_INCORRECT_ACCESS_LENGTH 0x2a006cUL
#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID 0x050054UL
#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 0x05004cUL
#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 0x050050UL
#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x2aa150UL
#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x2aa144UL
#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x2aa148UL
#define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x2aa14cUL
#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x2aa160UL
#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x2aa154UL
#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x2aa158UL
#define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x2aa15cUL
#define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL 0x2aa164UL
#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS 0x2aa54cUL
#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 0x2aa544UL
#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 0x2aa548UL
#define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 0x2aae80UL
#define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 0x2aae74UL
#define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 0x2aae78UL
#define PGLUE_B_REG_VF_ILT_ERR_DETAILS 0x2aae7cUL
#define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x2aa3bcUL
#define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT (0x1UL << 10)
#define DORQ_REG_DB_DROP_REASON 0x100a2cUL
#define DORQ_REG_DB_DROP_DETAILS 0x100a24UL
#define TM_REG_INT_STS_1 0x2c0190UL
#define TM_REG_INT_STS_1_PEND_TASK_SCAN (0x1UL << 6)
#define TM_REG_INT_STS_1_PEND_CONN_SCAN (0x1UL << 5)
#define TM_REG_INT_MASK_1 0x2c0194UL
#define TM_REG_INT_MASK_1_PEND_CONN_SCAN (0x1UL << 5)
#define TM_REG_INT_MASK_1_PEND_TASK_SCAN (0x1UL << 6)
#define MISC_REG_AEU_AFTER_INVERT_1_IGU 0x0087b4UL
#define MISC_REG_AEU_ENABLE4_IGU_OUT_0 0x0084a8UL
#define MISC_REG_AEU_ENABLE3_IGU_OUT_0 0x0084a4UL
#define YSEM_REG_FAST_MEMORY 0x1540000UL
#define NIG_REG_FLOWCTRL_MODE 0x501ba0UL
#define TSEM_REG_FAST_MEMORY 0x1740000UL
#define TSEM_REG_DBG_FRAME_MODE 0x1701408UL
#define TSEM_REG_SLOW_DBG_ACTIVE 0x1701400UL
#define TSEM_REG_SLOW_DBG_MODE 0x1701404UL
#define TSEM_REG_DBG_MODE1_CFG 0x1701420UL
#define TSEM_REG_SYNC_DBG_EMPTY 0x1701160UL
#define TSEM_REG_SLOW_DBG_EMPTY 0x1701140UL
#define TCM_REG_CTX_RBC_ACCS 0x11814c0UL
#define TCM_REG_AGG_CON_CTX 0x11814c4UL
#define TCM_REG_SM_CON_CTX 0x11814ccUL
#define TCM_REG_AGG_TASK_CTX 0x11814c8UL
#define TCM_REG_SM_TASK_CTX 0x11814d0UL
#define MSEM_REG_FAST_MEMORY 0x1840000UL
#define MSEM_REG_DBG_FRAME_MODE 0x1801408UL
#define MSEM_REG_SLOW_DBG_ACTIVE 0x1801400UL
#define MSEM_REG_SLOW_DBG_MODE 0x1801404UL
#define MSEM_REG_DBG_MODE1_CFG 0x1801420UL
#define MSEM_REG_SYNC_DBG_EMPTY 0x1801160UL
#define MSEM_REG_SLOW_DBG_EMPTY 0x1801140UL
#define MCM_REG_CTX_RBC_ACCS 0x1201800UL
#define MCM_REG_AGG_CON_CTX 0x1201804UL
#define MCM_REG_SM_CON_CTX 0x120180cUL
#define MCM_REG_AGG_TASK_CTX 0x1201808UL
#define MCM_REG_SM_TASK_CTX 0x1201810UL
#define USEM_REG_FAST_MEMORY 0x1940000UL
#define USEM_REG_DBG_FRAME_MODE 0x1901408UL
#define USEM_REG_SLOW_DBG_ACTIVE 0x1901400UL
#define USEM_REG_SLOW_DBG_MODE 0x1901404UL
#define USEM_REG_DBG_MODE1_CFG 0x1901420UL
#define USEM_REG_SYNC_DBG_EMPTY 0x1901160UL
#define USEM_REG_SLOW_DBG_EMPTY 0x1901140UL
#define UCM_REG_CTX_RBC_ACCS 0x1281700UL
#define UCM_REG_AGG_CON_CTX 0x1281704UL
#define UCM_REG_SM_CON_CTX 0x128170cUL
#define UCM_REG_AGG_TASK_CTX 0x1281708UL
#define UCM_REG_SM_TASK_CTX 0x1281710UL
#define XSEM_REG_FAST_MEMORY 0x1440000UL
#define XSEM_REG_DBG_FRAME_MODE 0x1401408UL
#define XSEM_REG_SLOW_DBG_ACTIVE 0x1401400UL
#define XSEM_REG_SLOW_DBG_MODE 0x1401404UL
#define XSEM_REG_DBG_MODE1_CFG 0x1401420UL
#define XSEM_REG_SYNC_DBG_EMPTY 0x1401160UL
#define XSEM_REG_SLOW_DBG_EMPTY 0x1401140UL
#define XCM_REG_CTX_RBC_ACCS 0x1001800UL
#define XCM_REG_AGG_CON_CTX 0x1001804UL
#define XCM_REG_SM_CON_CTX 0x1001808UL
#define YSEM_REG_DBG_FRAME_MODE 0x1501408UL
#define YSEM_REG_SLOW_DBG_ACTIVE 0x1501400UL
#define YSEM_REG_SLOW_DBG_MODE 0x1501404UL
#define YSEM_REG_DBG_MODE1_CFG 0x1501420UL
#define YSEM_REG_SYNC_DBG_EMPTY 0x1501160UL
#define YCM_REG_CTX_RBC_ACCS 0x1081800UL
#define YCM_REG_AGG_CON_CTX 0x1081804UL
#define YCM_REG_SM_CON_CTX 0x108180cUL
#define YCM_REG_AGG_TASK_CTX 0x1081808UL
#define YCM_REG_SM_TASK_CTX 0x1081810UL
#define PSEM_REG_FAST_MEMORY 0x1640000UL
#define PSEM_REG_DBG_FRAME_MODE 0x1601408UL
#define PSEM_REG_SLOW_DBG_ACTIVE 0x1601400UL
#define PSEM_REG_SLOW_DBG_MODE 0x1601404UL
#define PSEM_REG_DBG_MODE1_CFG 0x1601420UL
#define PSEM_REG_SYNC_DBG_EMPTY 0x1601160UL
#define PSEM_REG_SLOW_DBG_EMPTY 0x1601140UL
#define PCM_REG_CTX_RBC_ACCS 0x1101440UL
#define PCM_REG_SM_CON_CTX 0x1101444UL
#define GRC_REG_DBG_SELECT 0x0500a4UL
#define GRC_REG_DBG_DWORD_ENABLE 0x0500a8UL
#define GRC_REG_DBG_SHIFT 0x0500acUL
#define GRC_REG_DBG_FORCE_VALID 0x0500b0UL
#define GRC_REG_DBG_FORCE_FRAME 0x0500b4UL
#define PGLUE_B_REG_DBG_SELECT 0x2a8400UL
#define PGLUE_B_REG_DBG_DWORD_ENABLE 0x2a8404UL
#define PGLUE_B_REG_DBG_SHIFT 0x2a8408UL
#define PGLUE_B_REG_DBG_FORCE_VALID 0x2a840cUL
#define PGLUE_B_REG_DBG_FORCE_FRAME 0x2a8410UL
#define CNIG_REG_DBG_SELECT_K2 0x218254UL
#define CNIG_REG_DBG_DWORD_ENABLE_K2 0x218258UL
#define CNIG_REG_DBG_SHIFT_K2 0x21825cUL
#define CNIG_REG_DBG_FORCE_VALID_K2 0x218260UL
#define CNIG_REG_DBG_FORCE_FRAME_K2 0x218264UL
#define NCSI_REG_DBG_SELECT 0x040474UL
#define NCSI_REG_DBG_DWORD_ENABLE 0x040478UL
#define NCSI_REG_DBG_SHIFT 0x04047cUL
#define NCSI_REG_DBG_FORCE_VALID 0x040480UL
#define NCSI_REG_DBG_FORCE_FRAME 0x040484UL
#define BMB_REG_DBG_SELECT 0x540a7cUL
#define BMB_REG_DBG_DWORD_ENABLE 0x540a80UL
#define BMB_REG_DBG_SHIFT 0x540a84UL
#define BMB_REG_DBG_FORCE_VALID 0x540a88UL
#define BMB_REG_DBG_FORCE_FRAME 0x540a8cUL
#define PCIE_REG_DBG_SELECT 0x0547e8UL
#define PHY_PCIE_REG_DBG_SELECT 0x629fe8UL
#define PCIE_REG_DBG_DWORD_ENABLE 0x0547ecUL
#define PHY_PCIE_REG_DBG_DWORD_ENABLE 0x629fecUL
#define PCIE_REG_DBG_SHIFT 0x0547f0UL
#define PHY_PCIE_REG_DBG_SHIFT 0x629ff0UL
#define PCIE_REG_DBG_FORCE_VALID 0x0547f4UL
#define PHY_PCIE_REG_DBG_FORCE_VALID 0x629ff4UL
#define PCIE_REG_DBG_FORCE_FRAME 0x0547f8UL
#define PHY_PCIE_REG_DBG_FORCE_FRAME 0x629ff8UL
#define MCP2_REG_DBG_SELECT 0x052400UL
#define MCP2_REG_DBG_SHIFT 0x052408UL
#define MCP2_REG_DBG_FORCE_VALID 0x052440UL
#define MCP2_REG_DBG_FORCE_FRAME 0x052444UL
#define PSWHST_REG_DBG_SELECT 0x2a0100UL
#define PSWHST_REG_DBG_DWORD_ENABLE 0x2a0104UL
#define PSWHST_REG_DBG_SHIFT 0x2a0108UL
#define PSWHST_REG_DBG_FORCE_VALID 0x2a010cUL
#define PSWHST_REG_DBG_FORCE_FRAME 0x2a0110UL
#define PSWHST2_REG_DBG_SELECT 0x29e058UL
#define PSWHST2_REG_DBG_DWORD_ENABLE 0x29e05cUL
#define PSWHST2_REG_DBG_SHIFT 0x29e060UL
#define PSWHST2_REG_DBG_FORCE_VALID 0x29e064UL
#define PSWHST2_REG_DBG_FORCE_FRAME 0x29e068UL
#define PSWRD_REG_DBG_DWORD_ENABLE 0x29c044UL
#define PSWRD_REG_DBG_SHIFT 0x29c048UL
#define PSWRD_REG_DBG_FORCE_VALID 0x29c04cUL
#define PSWRD_REG_DBG_FORCE_FRAME 0x29c050UL
#define PSWRD2_REG_DBG_SELECT 0x29d400UL
#define PSWRD2_REG_DBG_DWORD_ENABLE 0x29d404UL
#define PSWRD2_REG_DBG_SHIFT 0x29d408UL
#define PSWRD2_REG_DBG_FORCE_VALID 0x29d40cUL
#define PSWRD2_REG_DBG_FORCE_FRAME 0x29d410UL
#define PSWWR_REG_DBG_SELECT 0x29a084UL
#define PSWWR_REG_DBG_DWORD_ENABLE 0x29a088UL
#define PSWWR_REG_DBG_SHIFT 0x29a08cUL
#define PSWWR_REG_DBG_FORCE_VALID 0x29a090UL
#define PSWWR_REG_DBG_FORCE_FRAME 0x29a094UL
#define PSWRQ_REG_DBG_DWORD_ENABLE 0x280024UL
#define PSWRQ_REG_DBG_SHIFT 0x280028UL
#define PSWRQ_REG_DBG_FORCE_VALID 0x28002cUL
#define PSWRQ_REG_DBG_FORCE_FRAME 0x280030UL
#define PSWRQ2_REG_DBG_SELECT 0x240100UL
#define PSWRQ2_REG_DBG_DWORD_ENABLE 0x240104UL
#define PSWRQ2_REG_DBG_SHIFT 0x240108UL
#define PSWRQ2_REG_DBG_FORCE_VALID 0x24010cUL
#define PSWRQ2_REG_DBG_FORCE_FRAME 0x240110UL
#define PGLCS_REG_DBG_SELECT 0x001d14UL
#define PGLCS_REG_DBG_DWORD_ENABLE 0x001d18UL
#define PGLCS_REG_DBG_SHIFT 0x001d1cUL
#define PGLCS_REG_DBG_FORCE_VALID 0x001d20UL
#define PGLCS_REG_DBG_FORCE_FRAME 0x001d24UL
#define PTU_REG_DBG_SELECT 0x560100UL
#define PTU_REG_DBG_DWORD_ENABLE 0x560104UL
#define PTU_REG_DBG_SHIFT 0x560108UL
#define PTU_REG_DBG_FORCE_VALID 0x56010cUL
#define PTU_REG_DBG_FORCE_FRAME 0x560110UL
#define DMAE_REG_DBG_SELECT 0x00c510UL
#define DMAE_REG_DBG_DWORD_ENABLE 0x00c514UL
#define DMAE_REG_DBG_SHIFT 0x00c518UL
#define DMAE_REG_DBG_FORCE_VALID 0x00c51cUL
#define DMAE_REG_DBG_FORCE_FRAME 0x00c520UL
#define TCM_REG_DBG_SELECT 0x1180040UL
#define TCM_REG_DBG_DWORD_ENABLE 0x1180044UL
#define TCM_REG_DBG_SHIFT 0x1180048UL
#define TCM_REG_DBG_FORCE_VALID 0x118004cUL
#define TCM_REG_DBG_FORCE_FRAME 0x1180050UL
#define MCM_REG_DBG_SELECT 0x1200040UL
#define MCM_REG_DBG_DWORD_ENABLE 0x1200044UL
#define MCM_REG_DBG_SHIFT 0x1200048UL
#define MCM_REG_DBG_FORCE_VALID 0x120004cUL
#define MCM_REG_DBG_FORCE_FRAME 0x1200050UL
#define UCM_REG_DBG_SELECT 0x1280050UL
#define UCM_REG_DBG_DWORD_ENABLE 0x1280054UL
#define UCM_REG_DBG_SHIFT 0x1280058UL
#define UCM_REG_DBG_FORCE_VALID 0x128005cUL
#define UCM_REG_DBG_FORCE_FRAME 0x1280060UL
#define XCM_REG_DBG_SELECT 0x1000040UL
#define XCM_REG_DBG_DWORD_ENABLE 0x1000044UL
#define XCM_REG_DBG_SHIFT 0x1000048UL
#define XCM_REG_DBG_FORCE_VALID 0x100004cUL
#define XCM_REG_DBG_FORCE_FRAME 0x1000050UL
#define YCM_REG_DBG_SELECT 0x1080040UL
#define YCM_REG_DBG_DWORD_ENABLE 0x1080044UL
#define YCM_REG_DBG_SHIFT 0x1080048UL
#define YCM_REG_DBG_FORCE_VALID 0x108004cUL
#define YCM_REG_DBG_FORCE_FRAME 0x1080050UL
#define PCM_REG_DBG_SELECT 0x1100040UL
#define PCM_REG_DBG_DWORD_ENABLE 0x1100044UL
#define PCM_REG_DBG_SHIFT 0x1100048UL
#define PCM_REG_DBG_FORCE_VALID 0x110004cUL
#define PCM_REG_DBG_FORCE_FRAME 0x1100050UL
#define QM_REG_DBG_SELECT 0x2f2e74UL
#define QM_REG_DBG_DWORD_ENABLE 0x2f2e78UL
#define QM_REG_DBG_SHIFT 0x2f2e7cUL
#define QM_REG_DBG_FORCE_VALID 0x2f2e80UL
#define QM_REG_DBG_FORCE_FRAME 0x2f2e84UL
#define TM_REG_DBG_SELECT 0x2c07a8UL
#define TM_REG_DBG_DWORD_ENABLE 0x2c07acUL
#define TM_REG_DBG_SHIFT 0x2c07b0UL
#define TM_REG_DBG_FORCE_VALID 0x2c07b4UL
#define TM_REG_DBG_FORCE_FRAME 0x2c07b8UL
#define DORQ_REG_DBG_SELECT 0x100ad0UL
#define DORQ_REG_DBG_DWORD_ENABLE 0x100ad4UL
#define DORQ_REG_DBG_SHIFT 0x100ad8UL
#define DORQ_REG_DBG_FORCE_VALID 0x100adcUL
#define DORQ_REG_DBG_FORCE_FRAME 0x100ae0UL
#define BRB_REG_DBG_SELECT 0x340ed0UL
#define BRB_REG_DBG_DWORD_ENABLE 0x340ed4UL
#define BRB_REG_DBG_SHIFT 0x340ed8UL
#define BRB_REG_DBG_FORCE_VALID 0x340edcUL
#define BRB_REG_DBG_FORCE_FRAME 0x340ee0UL
#define SRC_REG_DBG_SELECT 0x238700UL
#define SRC_REG_DBG_DWORD_ENABLE 0x238704UL
#define SRC_REG_DBG_SHIFT 0x238708UL
#define SRC_REG_DBG_FORCE_VALID 0x23870cUL
#define SRC_REG_DBG_FORCE_FRAME 0x238710UL
#define PRS_REG_DBG_SELECT 0x1f0b6cUL
#define PRS_REG_DBG_DWORD_ENABLE 0x1f0b70UL
#define PRS_REG_DBG_SHIFT 0x1f0b74UL
#define PRS_REG_DBG_FORCE_VALID 0x1f0ba0UL
#define PRS_REG_DBG_FORCE_FRAME 0x1f0ba4UL
#define TSDM_REG_DBG_SELECT 0xfb0e28UL
#define TSDM_REG_DBG_DWORD_ENABLE 0xfb0e2cUL
#define TSDM_REG_DBG_SHIFT 0xfb0e30UL
#define TSDM_REG_DBG_FORCE_VALID 0xfb0e34UL
#define TSDM_REG_DBG_FORCE_FRAME 0xfb0e38UL
#define MSDM_REG_DBG_SELECT 0xfc0e28UL
#define MSDM_REG_DBG_DWORD_ENABLE 0xfc0e2cUL
#define MSDM_REG_DBG_SHIFT 0xfc0e30UL
#define MSDM_REG_DBG_FORCE_VALID 0xfc0e34UL
#define MSDM_REG_DBG_FORCE_FRAME 0xfc0e38UL
#define USDM_REG_DBG_SELECT 0xfd0e28UL
#define USDM_REG_DBG_DWORD_ENABLE 0xfd0e2cUL
#define USDM_REG_DBG_SHIFT 0xfd0e30UL
#define USDM_REG_DBG_FORCE_VALID 0xfd0e34UL
#define USDM_REG_DBG_FORCE_FRAME 0xfd0e38UL
#define XSDM_REG_DBG_SELECT 0xf80e28UL
#define XSDM_REG_DBG_DWORD_ENABLE 0xf80e2cUL
#define XSDM_REG_DBG_SHIFT 0xf80e30UL
#define XSDM_REG_DBG_FORCE_VALID 0xf80e34UL
#define XSDM_REG_DBG_FORCE_FRAME 0xf80e38UL
#define YSDM_REG_DBG_SELECT 0xf90e28UL
#define YSDM_REG_DBG_DWORD_ENABLE 0xf90e2cUL
#define YSDM_REG_DBG_SHIFT 0xf90e30UL
#define YSDM_REG_DBG_FORCE_VALID 0xf90e34UL
#define YSDM_REG_DBG_FORCE_FRAME 0xf90e38UL
#define PSDM_REG_DBG_SELECT 0xfa0e28UL
#define PSDM_REG_DBG_DWORD_ENABLE 0xfa0e2cUL
#define PSDM_REG_DBG_SHIFT 0xfa0e30UL
#define PSDM_REG_DBG_FORCE_VALID 0xfa0e34UL
#define PSDM_REG_DBG_FORCE_FRAME 0xfa0e38UL
#define TSEM_REG_DBG_SELECT 0x1701528UL
#define TSEM_REG_DBG_DWORD_ENABLE 0x170152cUL
#define TSEM_REG_DBG_SHIFT 0x1701530UL
#define TSEM_REG_DBG_FORCE_VALID 0x1701534UL
#define TSEM_REG_DBG_FORCE_FRAME 0x1701538UL
#define MSEM_REG_DBG_SELECT 0x1801528UL
#define MSEM_REG_DBG_DWORD_ENABLE 0x180152cUL
#define MSEM_REG_DBG_SHIFT 0x1801530UL
#define MSEM_REG_DBG_FORCE_VALID 0x1801534UL
#define MSEM_REG_DBG_FORCE_FRAME 0x1801538UL
#define USEM_REG_DBG_SELECT 0x1901528UL
#define USEM_REG_DBG_DWORD_ENABLE 0x190152cUL
#define USEM_REG_DBG_SHIFT 0x1901530UL
#define USEM_REG_DBG_FORCE_VALID 0x1901534UL
#define USEM_REG_DBG_FORCE_FRAME 0x1901538UL
#define XSEM_REG_DBG_SELECT 0x1401528UL
#define XSEM_REG_DBG_DWORD_ENABLE 0x140152cUL
#define XSEM_REG_DBG_SHIFT 0x1401530UL
#define XSEM_REG_DBG_FORCE_VALID 0x1401534UL
#define XSEM_REG_DBG_FORCE_FRAME 0x1401538UL
#define YSEM_REG_DBG_SELECT 0x1501528UL
#define YSEM_REG_DBG_DWORD_ENABLE 0x150152cUL
#define YSEM_REG_DBG_SHIFT 0x1501530UL
#define YSEM_REG_DBG_FORCE_VALID 0x1501534UL
#define YSEM_REG_DBG_FORCE_FRAME 0x1501538UL
#define PSEM_REG_DBG_SELECT 0x1601528UL
#define PSEM_REG_DBG_DWORD_ENABLE 0x160152cUL
#define PSEM_REG_DBG_SHIFT 0x1601530UL
#define PSEM_REG_DBG_FORCE_VALID 0x1601534UL
#define PSEM_REG_DBG_FORCE_FRAME 0x1601538UL
#define RSS_REG_DBG_SELECT 0x238c4cUL
#define RSS_REG_DBG_DWORD_ENABLE 0x238c50UL
#define RSS_REG_DBG_SHIFT 0x238c54UL
#define RSS_REG_DBG_FORCE_VALID 0x238c58UL
#define RSS_REG_DBG_FORCE_FRAME 0x238c5cUL
#define TMLD_REG_DBG_SELECT 0x4d1600UL
#define TMLD_REG_DBG_DWORD_ENABLE 0x4d1604UL
#define TMLD_REG_DBG_SHIFT 0x4d1608UL
#define TMLD_REG_DBG_FORCE_VALID 0x4d160cUL
#define TMLD_REG_DBG_FORCE_FRAME 0x4d1610UL
#define MULD_REG_DBG_SELECT 0x4e1600UL
#define MULD_REG_DBG_DWORD_ENABLE 0x4e1604UL
#define MULD_REG_DBG_SHIFT 0x4e1608UL
#define MULD_REG_DBG_FORCE_VALID 0x4e160cUL
#define MULD_REG_DBG_FORCE_FRAME 0x4e1610UL
#define YULD_REG_DBG_SELECT 0x4c9600UL
#define YULD_REG_DBG_DWORD_ENABLE 0x4c9604UL
#define YULD_REG_DBG_SHIFT 0x4c9608UL
#define YULD_REG_DBG_FORCE_VALID 0x4c960cUL
#define YULD_REG_DBG_FORCE_FRAME 0x4c9610UL
#define XYLD_REG_DBG_SELECT 0x4c1600UL
#define XYLD_REG_DBG_DWORD_ENABLE 0x4c1604UL
#define XYLD_REG_DBG_SHIFT 0x4c1608UL
#define XYLD_REG_DBG_FORCE_VALID 0x4c160cUL
#define XYLD_REG_DBG_FORCE_FRAME 0x4c1610UL
#define PRM_REG_DBG_SELECT 0x2306a8UL
#define PRM_REG_DBG_DWORD_ENABLE 0x2306acUL
#define PRM_REG_DBG_SHIFT 0x2306b0UL
#define PRM_REG_DBG_FORCE_VALID 0x2306b4UL
#define PRM_REG_DBG_FORCE_FRAME 0x2306b8UL
#define PBF_PB1_REG_DBG_SELECT 0xda0728UL
#define PBF_PB1_REG_DBG_DWORD_ENABLE 0xda072cUL
#define PBF_PB1_REG_DBG_SHIFT 0xda0730UL
#define PBF_PB1_REG_DBG_FORCE_VALID 0xda0734UL
#define PBF_PB1_REG_DBG_FORCE_FRAME 0xda0738UL
#define PBF_PB2_REG_DBG_SELECT 0xda4728UL
#define PBF_PB2_REG_DBG_DWORD_ENABLE 0xda472cUL
#define PBF_PB2_REG_DBG_SHIFT 0xda4730UL
#define PBF_PB2_REG_DBG_FORCE_VALID 0xda4734UL
#define PBF_PB2_REG_DBG_FORCE_FRAME 0xda4738UL
#define RPB_REG_DBG_SELECT 0x23c728UL
#define RPB_REG_DBG_DWORD_ENABLE 0x23c72cUL
#define RPB_REG_DBG_SHIFT 0x23c730UL
#define RPB_REG_DBG_FORCE_VALID 0x23c734UL
#define RPB_REG_DBG_FORCE_FRAME 0x23c738UL
#define BTB_REG_DBG_SELECT 0xdb08c8UL
#define BTB_REG_DBG_DWORD_ENABLE 0xdb08ccUL
#define BTB_REG_DBG_SHIFT 0xdb08d0UL
#define BTB_REG_DBG_FORCE_VALID 0xdb08d4UL
#define BTB_REG_DBG_FORCE_FRAME 0xdb08d8UL
#define PBF_REG_DBG_SELECT 0xd80060UL
#define PBF_REG_DBG_DWORD_ENABLE 0xd80064UL
#define PBF_REG_DBG_SHIFT 0xd80068UL
#define PBF_REG_DBG_FORCE_VALID 0xd8006cUL
#define PBF_REG_DBG_FORCE_FRAME 0xd80070UL
#define RDIF_REG_DBG_SELECT 0x300500UL
#define RDIF_REG_DBG_DWORD_ENABLE 0x300504UL
#define RDIF_REG_DBG_SHIFT 0x300508UL
#define RDIF_REG_DBG_FORCE_VALID 0x30050cUL
#define RDIF_REG_DBG_FORCE_FRAME 0x300510UL
#define TDIF_REG_DBG_SELECT 0x310500UL
#define TDIF_REG_DBG_DWORD_ENABLE 0x310504UL
#define TDIF_REG_DBG_SHIFT 0x310508UL
#define TDIF_REG_DBG_FORCE_VALID 0x31050cUL
#define TDIF_REG_DBG_FORCE_FRAME 0x310510UL
#define CDU_REG_DBG_SELECT 0x580704UL
#define CDU_REG_DBG_DWORD_ENABLE 0x580708UL
#define CDU_REG_DBG_SHIFT 0x58070cUL
#define CDU_REG_DBG_FORCE_VALID 0x580710UL
#define CDU_REG_DBG_FORCE_FRAME 0x580714UL
#define CCFC_REG_DBG_SELECT 0x2e0500UL
#define CCFC_REG_DBG_DWORD_ENABLE 0x2e0504UL
#define CCFC_REG_DBG_SHIFT 0x2e0508UL
#define CCFC_REG_DBG_FORCE_VALID 0x2e050cUL
#define CCFC_REG_DBG_FORCE_FRAME 0x2e0510UL
#define TCFC_REG_DBG_SELECT 0x2d0500UL
#define TCFC_REG_DBG_DWORD_ENABLE 0x2d0504UL
#define TCFC_REG_DBG_SHIFT 0x2d0508UL
#define TCFC_REG_DBG_FORCE_VALID 0x2d050cUL
#define TCFC_REG_DBG_FORCE_FRAME 0x2d0510UL
#define IGU_REG_DBG_SELECT 0x181578UL
#define IGU_REG_DBG_DWORD_ENABLE 0x18157cUL
#define IGU_REG_DBG_SHIFT 0x181580UL
#define IGU_REG_DBG_FORCE_VALID 0x181584UL
#define IGU_REG_DBG_FORCE_FRAME 0x181588UL
#define CAU_REG_DBG_SELECT 0x1c0ea8UL
#define CAU_REG_DBG_DWORD_ENABLE 0x1c0eacUL
#define CAU_REG_DBG_SHIFT 0x1c0eb0UL
#define CAU_REG_DBG_FORCE_VALID 0x1c0eb4UL
#define CAU_REG_DBG_FORCE_FRAME 0x1c0eb8UL
#define UMAC_REG_DBG_SELECT 0x051094UL
#define UMAC_REG_DBG_DWORD_ENABLE 0x051098UL
#define UMAC_REG_DBG_SHIFT 0x05109cUL
#define UMAC_REG_DBG_FORCE_VALID 0x0510a0UL
#define UMAC_REG_DBG_FORCE_FRAME 0x0510a4UL
#define NIG_REG_DBG_SELECT 0x502140UL
#define NIG_REG_DBG_DWORD_ENABLE 0x502144UL
#define NIG_REG_DBG_SHIFT 0x502148UL
#define NIG_REG_DBG_FORCE_VALID 0x50214cUL
#define NIG_REG_DBG_FORCE_FRAME 0x502150UL
#define WOL_REG_DBG_SELECT 0x600140UL
#define WOL_REG_DBG_DWORD_ENABLE 0x600144UL
#define WOL_REG_DBG_SHIFT 0x600148UL
#define WOL_REG_DBG_FORCE_VALID 0x60014cUL
#define WOL_REG_DBG_FORCE_FRAME 0x600150UL
#define BMBN_REG_DBG_SELECT 0x610140UL
#define BMBN_REG_DBG_DWORD_ENABLE 0x610144UL
#define BMBN_REG_DBG_SHIFT 0x610148UL
#define BMBN_REG_DBG_FORCE_VALID 0x61014cUL
#define BMBN_REG_DBG_FORCE_FRAME 0x610150UL
#define NWM_REG_DBG_SELECT 0x8000ecUL
#define NWM_REG_DBG_DWORD_ENABLE 0x8000f0UL
#define NWM_REG_DBG_SHIFT 0x8000f4UL
#define NWM_REG_DBG_FORCE_VALID 0x8000f8UL
#define NWM_REG_DBG_FORCE_FRAME 0x8000fcUL
#define BRB_REG_BIG_RAM_ADDRESS 0x340800UL
#define BRB_REG_BIG_RAM_DATA 0x341500UL
#define BTB_REG_BIG_RAM_ADDRESS 0xdb0800UL
#define BTB_REG_BIG_RAM_DATA 0xdb0c00UL
#define BMB_REG_BIG_RAM_ADDRESS 0x540800UL
#define BMB_REG_BIG_RAM_DATA 0x540f00UL
#define MISCS_REG_RESET_PL_UA 0x009050UL
#define MISC_REG_RESET_PL_UA 0x008050UL
#define MISC_REG_RESET_PL_HV 0x008060UL
#define MISC_REG_RESET_PL_PDA_VMAIN_1 0x008070UL
#define MISC_REG_RESET_PL_PDA_VMAIN_2 0x008080UL
#define SEM_FAST_REG_INT_RAM 0x020000UL
#define DBG_REG_DBG_BLOCK_ON 0x010454UL
#define DBG_REG_FRAMING_MODE 0x010058UL
#define SEM_FAST_REG_DEBUG_MODE 0x000744UL
#define SEM_FAST_REG_DEBUG_ACTIVE 0x000740UL
#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE 0x000750UL
#define SEM_FAST_REG_FILTER_CID 0x000754UL
#define SEM_FAST_REG_EVENT_ID_RANGE_STRT 0x000760UL
#define SEM_FAST_REG_EVENT_ID_RANGE_END 0x000764UL
#define SEM_FAST_REG_FILTER_EVENT_ID 0x000758UL
#define SEM_FAST_REG_EVENT_ID_MASK 0x00075cUL
#define SEM_FAST_REG_RECORD_FILTER_ENABLE 0x000768UL
#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE 0x000750UL
#define SEM_FAST_REG_DEBUG_ACTIVE 0x000740UL
#define SEM_FAST_REG_RECORD_FILTER_ENABLE 0x000768UL
#define DBG_REG_TIMESTAMP_VALID_EN 0x010b58UL
#define DBG_REG_FILTER_ENABLE 0x0109d0UL
#define DBG_REG_TRIGGER_ENABLE 0x01054cUL
#define DBG_REG_FILTER_CNSTR_OPRTN_0 0x010a28UL
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_0 0x01071cUL
#define DBG_REG_FILTER_CNSTR_DATA_0 0x0109d8UL
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_0 0x01059cUL
#define DBG_REG_FILTER_CNSTR_DATA_MASK_0 0x0109f8UL
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_0 0x01065cUL
#define DBG_REG_FILTER_CNSTR_FRAME_0 0x0109e8UL
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_0 0x0105fcUL
#define DBG_REG_FILTER_CNSTR_FRAME_MASK_0 0x010a08UL
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0 0x0106bcUL
#define DBG_REG_FILTER_CNSTR_OFFSET_0 0x010a18UL
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0 0x0107dcUL
#define DBG_REG_FILTER_CNSTR_RANGE_0 0x010a38UL
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0 0x01077cUL
#define DBG_REG_FILTER_CNSTR_CYCLIC_0 0x010a68UL
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_0 0x0108fcUL
#define DBG_REG_FILTER_CNSTR_MUST_0 0x010a48UL
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_0 0x01083cUL
#define DBG_REG_INTR_BUFFER 0x014000UL
#define DBG_REG_INTR_BUFFER_WR_PTR 0x010404UL
#define DBG_REG_WRAP_ON_INT_BUFFER 0x010418UL
#define DBG_REG_INTR_BUFFER_RD_PTR 0x010400UL
#define DBG_REG_EXT_BUFFER_WR_PTR 0x010410UL
#define DBG_REG_WRAP_ON_EXT_BUFFER 0x01041cUL
#define SEM_FAST_REG_STALL_0 0x000488UL
#define SEM_FAST_REG_STALLED 0x000494UL
#define SEM_FAST_REG_STORM_REG_FILE 0x008000UL
#define SEM_FAST_REG_VFC_DATA_WR 0x000b40UL
#define SEM_FAST_REG_VFC_ADDR 0x000b44UL
#define SEM_FAST_REG_VFC_DATA_RD 0x000b48UL
#define SEM_FAST_REG_VFC_DATA_WR 0x000b40UL
#define SEM_FAST_REG_VFC_ADDR 0x000b44UL
#define SEM_FAST_REG_VFC_DATA_RD 0x000b48UL
#define RSS_REG_RSS_RAM_ADDR 0x238c30UL
#define RSS_REG_RSS_RAM_DATA 0x238c20UL
#define MISCS_REG_BLOCK_256B_EN 0x009074UL
#define MCP_REG_CPU_REG_FILE 0xe05200UL
#define MCP_REG_CPU_REG_FILE_SIZE 32
#define DBG_REG_CALENDAR_OUT_DATA 0x010480UL
#define DBG_REG_FULL_MODE 0x010060UL
#define DBG_REG_PCI_EXT_BUFFER_STRT_ADDR_LSB 0x010430UL
#define DBG_REG_PCI_EXT_BUFFER_STRT_ADDR_MSB 0x010434UL
#define DBG_REG_TARGET_PACKET_SIZE 0x010b3cUL
#define DBG_REG_PCI_EXT_BUFFER_SIZE 0x010438UL
#define DBG_REG_PCI_FUNC_NUM 0x010a98UL
#define DBG_REG_PCI_LOGIC_ADDR 0x010460UL
#define DBG_REG_PCI_REQ_CREDIT 0x010440UL
#define DBG_REG_DEBUG_TARGET 0x01005cUL
#define DBG_REG_OUTPUT_ENABLE 0x01000cUL
#define DBG_REG_OUTPUT_ENABLE 0x01000cUL
#define DBG_REG_DEBUG_TARGET 0x01005cUL
#define DBG_REG_OTHER_ENGINE_MODE 0x010010UL
#define NIG_REG_DEBUG_PORT 0x5020d0UL
#define DBG_REG_ETHERNET_HDR_WIDTH 0x010b38UL
#define DBG_REG_ETHERNET_HDR_7 0x010b34UL
#define DBG_REG_ETHERNET_HDR_6 0x010b30UL
#define DBG_REG_ETHERNET_HDR_5 0x010b2cUL
#define DBG_REG_ETHERNET_HDR_4 0x010b28UL
#define DBG_REG_TARGET_PACKET_SIZE 0x010b3cUL
#define DBG_REG_NIG_DATA_LIMIT_SIZE 0x01043cUL
#define DBG_REG_TIMESTAMP_VALID_EN 0x010b58UL
#define DBG_REG_TIMESTAMP_FRAME_EN 0x010b54UL
#define DBG_REG_TIMESTAMP_TICK 0x010b50UL
#define DBG_REG_FILTER_ID_NUM 0x0109d4UL
#define DBG_REG_FILTER_MSG_LENGTH_ENABLE 0x010a78UL
#define DBG_REG_FILTER_MSG_LENGTH 0x010a7cUL
#define DBG_REG_RCRD_ON_WINDOW_PRE_NUM_CHUNKS 0x010a90UL
#define DBG_REG_RCRD_ON_WINDOW_POST_NUM_CYCLES 0x010a94UL
#define DBG_REG_RCRD_ON_WINDOW_PRE_TRGR_EVNT_MODE 0x010a88UL
#define DBG_REG_RCRD_ON_WINDOW_POST_TRGR_EVNT_MODE 0x010a8cUL
#define DBG_REG_TRIGGER_ENABLE 0x01054cUL
#define DBG_REG_TRIGGER_STATE_ID_0 0x010554UL
#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_0 0x01095cUL
#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_0 0x010968UL
#define DBG_REG_TRIGGER_STATE_SET_COUNT_0 0x010584UL
#define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_0 0x01056cUL
#define DBG_REG_NO_GRANT_ON_FULL 0x010458UL
#define DBG_REG_STORM_ID_NUM 0x010b14UL
#define DBG_REG_CALENDAR_SLOT0 0x010014UL
#define DBG_REG_HW_ID_NUM 0x010b10UL
#define DBG_REG_FILTER_ENABLE 0x0109d0UL
#define DBG_REG_TIMESTAMP 0x010b4cUL
#define DBG_REG_CPU_TIMEOUT 0x010450UL
#define DBG_REG_TRIGGER_STATUS_CUR_STATE 0x010b60UL
#define GRC_REG_TRACE_FIFO_VALID_DATA 0x050064UL
#define GRC_REG_TRACE_FIFO 0x050068UL
#define IGU_REG_ERROR_HANDLING_DATA_VALID 0x181530UL
#define IGU_REG_ERROR_HANDLING_MEMORY 0x181520UL
#define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW 0x05040cUL
#define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW 0x05040cUL
#define GRC_REG_PROTECTION_OVERRIDE_WINDOW 0x050500UL
#define TSEM_REG_VF_ERROR 0x1700408UL
#define USEM_REG_VF_ERROR 0x1900408UL
#define MSEM_REG_VF_ERROR 0x1800408UL
#define XSEM_REG_VF_ERROR 0x1400408UL
#define YSEM_REG_VF_ERROR 0x1500408UL
#define PSEM_REG_VF_ERROR 0x1600408UL
#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x2aa118UL
#define IGU_REG_STATISTIC_NUM_VF_MSG_SENT 0x180408UL
#define IGU_REG_VF_CONFIGURATION 0x180804UL
#define PSWHST_REG_ZONE_PERMISSION_TABLE 0x2a0800UL
#define DORQ_REG_VF_USAGE_CNT 0x1009c4UL
#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 0xd806ccUL
#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 0xd806c8UL
#define PRS_REG_MSG_CT_MAIN_0 0x1f0a24UL
#define PRS_REG_MSG_CT_LB_0 0x1f0a28UL
#define BRB_REG_PER_TC_COUNTERS 0x341a00UL

/* added */
#define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL
#define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL
#define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL
#define MISCS_REG_FUNCTION_HIDE 0x0096f0UL
#define PCIE_REG_PRTY_MASK 0x0547b4UL
#define PGLUE_B_REG_VF_BAR0_SIZE_K2 0x2aaeb4UL
#define BAR0_MAP_REG_YSDM_RAM 0x1e80000UL
#define SEM_FAST_REG_INT_RAM_SIZE 20480
#define MCP_REG_SCRATCH_SIZE 57344

#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT 24
#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT 24
#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT 16
#define DORQ_REG_DB_DROP_DETAILS_ADDRESS 0x100a1cUL

/* 8.10.9.0 FW */
#define NIG_REG_VXLAN_CTRL 0x50105cUL
#define PRS_REG_SEARCH_ROCE 0x1f040cUL
#define PRS_REG_CM_HDR_GFT 0x1f11c8UL
#define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT 0
#define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT 8
#define CCFC_REG_WEAK_ENABLE_VF 0x2e0704UL
#define TCFC_REG_STRONG_ENABLE_VF 0x2d070cUL
#define TCFC_REG_WEAK_ENABLE_VF 0x2d0704UL
#define PRS_REG_SEARCH_GFT 0x1f11bcUL
#define PRS_REG_LOAD_L2_FILTER 0x1f0198UL
#define PRS_REG_GFT_CAM 0x1f1100UL
#define PRS_REG_GFT_PROFILE_MASK_RAM 0x1f1000UL
#define PGLUE_B_REG_MSDM_VF_SHIFT_B 0x2aa1c4UL
#define PGLUE_B_REG_MSDM_OFFSET_MASK_B 0x2aa1c0UL
#define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST 0x1f0a0cUL
#define PRS_REG_SEARCH_FCOE 0x1f0408UL
#define PGLUE_B_REG_PGL_ADDR_E8_F0_K2 0x2aaf98UL
#define NIG_REG_DSCP_TO_TC_MAP_ENABLE 0x5088f8UL
#define PGLUE_B_REG_PGL_ADDR_EC_F0_K2 0x2aaf9cUL
#define PGLUE_B_REG_PGL_ADDR_F0_F0_K2 0x2aafa0UL
#define PRS_REG_ROCE_DEST_QP_MAX_PF 0x1f0430UL
#define PGLUE_B_REG_PGL_ADDR_F4_F0_K2 0x2aafa4UL
#define IGU_REG_WRITE_DONE_PENDING 0x180900UL
#define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR 0x50196cUL
#define PRS_REG_MSG_INFO 0x1f0a1cUL
#define BAR0_MAP_REG_XSDM_RAM 0x1e00000UL

/* 8.18.7.0 FW */
#define BRB_REG_INT_MASK_10 0x3401b8UL

#define IGU_REG_PRODUCER_MEMORY 0x182000UL
#define IGU_REG_CONSUMER_MEM 0x183000UL

#define CDU_REG_CCFC_CTX_VALID0 0x580400UL
#define CDU_REG_CCFC_CTX_VALID1 0x580404UL
#define CDU_REG_TCFC_CTX_VALID0 0x580408UL

#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2 0x100930UL
#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2 0x10092cUL
#define CNIG_REG_NW_PORT_MODE_BB 0x218200UL
#define CNIG_REG_PMEG_IF_CMD_BB 0x21821cUL
#define CNIG_REG_PMEG_IF_ADDR_BB 0x218224UL
#define CNIG_REG_PMEG_IF_WRDATA_BB 0x218228UL
#define NWM_REG_MAC0_K2 0x800400UL
  #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_SHIFT 0
  #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_SHIFT 1
  #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_SHIFT 3
#define ETH_MAC_REG_XIF_MODE_K2 0x000080UL
  #define ETH_MAC_REG_XIF_MODE_XGMII_K2_SHIFT 0
#define ETH_MAC_REG_FRM_LENGTH_K2 0x000014UL
  #define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_SHIFT 0
#define ETH_MAC_REG_TX_IPG_LENGTH_K2 0x000044UL
  #define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_SHIFT 0
#define ETH_MAC_REG_RX_FIFO_SECTIONS_K2 0x00001cUL
  #define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_SHIFT 0
#define ETH_MAC_REG_TX_FIFO_SECTIONS_K2 0x000020UL
  #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_SHIFT 16
  #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_SHIFT 0
  #define ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2 (0x1 << 6)
  #define ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2_SHIFT 6
#define ETH_MAC_REG_COMMAND_CONFIG_K2 0x000008UL
#define MISC_REG_XMAC_CORE_PORT_MODE_BB 0x008c08UL
#define MISC_REG_XMAC_PHY_PORT_MODE_BB 0x008c04UL
#define XMAC_REG_MODE_BB 0x210008UL
#define XMAC_REG_RX_MAX_SIZE_BB  0x210040UL
#define XMAC_REG_TX_CTRL_LO_BB 0x210020UL
#define XMAC_REG_CTRL_BB 0x210000UL
#define XMAC_REG_CTRL_TX_EN_BB (0x1UL << 0)
#define XMAC_REG_CTRL_RX_EN_BB (0x1UL << 1)
#define XMAC_REG_RX_CTRL_BB 0x210030UL
#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB (0x1UL << 12)

#define PGLUE_B_REG_PGL_ADDR_88_F0_BB 0x2aa404UL
#define PGLUE_B_REG_PGL_ADDR_8C_F0_BB 0x2aa408UL
#define PGLUE_B_REG_PGL_ADDR_90_F0_BB 0x2aa40cUL
#define PGLUE_B_REG_PGL_ADDR_94_F0_BB 0x2aa410UL
#define MISCS_REG_FUNCTION_HIDE_BB_K2 0x0096f0UL
#define PCIE_REG_PRTY_MASK_K2 0x0547b4UL

#define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2 0x1f099cUL

#define NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 0x501a00UL
#define NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 0x501a80UL
#define NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 0x501ac0UL
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 0x501b00UL

#define PSWRQ2_REG_WR_MBS0 0x240400UL
#define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE 0x2aae30UL
#define DORQ_REG_PF_USAGE_CNT 0x1009c0UL
#define DORQ_REG_DPM_FORCE_ABORT 0x1009d8UL
#define DORQ_REG_PF_OVFL_STICKY 0x1009d0UL
#define DORQ_REG_INT_STS 0x100180UL
  #define DORQ_REG_INT_STS_DB_DROP (0x1UL << 1)
  #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR (0x1UL << 2)
  #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL (0x1UL << 3)
#define DORQ_REG_DB_DROP_DETAILS_REL 0x100a28UL
#define DORQ_REG_INT_STS_WR 0x100188UL
#define DORQ_REG_DB_DROP_DETAILS_REASON 0x100a20UL
#define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL
  #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1UL << 10)
#define PRS_REG_SEARCH_TENANT_ID 0x1f044cUL
#define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL

#define RSS_REG_RSS_RAM_MASK 0x238c10UL

#define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL
#define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL
#define DORQ_REG_TAG1_OVRD_MODE 0x1008b4UL
#define DORQ_REG_PF_PCP 0x1008c4UL
#define DORQ_REG_PF_EXT_VID 0x1008c8UL
#define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL
#define NIG_REG_LLH_PPFID2PFID_TBL_0 0x501970UL
#define NIG_REG_PPF_TO_ENGINE_SEL 0x508900UL
#define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL 0x501b98UL
#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL 0x501b40UL

#define MCP_REG_CACHE_PAGING_ENABLE 0xe06304UL
#define PSWRQ2_REG_RESET_STT 0x240008UL
#define PSWRQ2_REG_PRTY_STS_WR_H_0 0x240208UL
#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0
#define PGLUE_B_REG_MASTER_DISCARD_NBLOCK 0x2aa58cUL
#define PGLUE_B_REG_PRTY_STS_WR_H_0 0x2a8208UL
#define DORQ_REG_VF_USAGE_CNT_LIM 0x1009ccUL
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x2aa06cUL
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR 0x2aa070UL

#define PSWRQ2_REG_ILT_MEMORY_SIZE_BB 15200
#define PSWRQ2_REG_ILT_MEMORY_SIZE_K2 22000
#define TSEM_REG_DBG_GPRE_VECT 0x1701410UL
#define MSEM_REG_DBG_GPRE_VECT 0x1801410UL
#define USEM_REG_DBG_GPRE_VECT 0x1901410UL
#define XSEM_REG_DBG_GPRE_VECT 0x1401410UL
#define YSEM_REG_DBG_GPRE_VECT 0x1501410UL
#define PSEM_REG_DBG_GPRE_VECT 0x1601410UL
#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE 0x000748UL
  #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_DRA_WRITE_DISABLE (0x1UL << 0)
  #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_DRA_WRITE_DISABLE_SHIFT 0
  #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_DRA_READ_DISABLE (0x1UL << 1)
  #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_DRA_READ_DISABLE_SHIFT 1
  #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_INTERRUPT_DISABLE (0x1UL << 2)
  #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_INTERRUPT_DISABLE_SHIFT 2
#define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE 0x00074cUL
  #define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_STORE_DATA_DISABLE (0x1UL << 0)
  #define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_STORE_DATA_DISABLE_SHIFT 0
  #define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_LOAD_DATA_DISABLE (0x1UL << 1)
  #define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_LOAD_DATA_DISABLE_SHIFT 1
#define NWS_REG_NWS_CMU_K2 0x720000UL
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2 0x000680UL
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2 0x000684UL
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2 0x0006c0UL
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2 0x0006c4UL
#define MS_REG_MS_CMU_K2 0x6a4000UL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2 0x000210UL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2 0x000214UL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2 0x000208UL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2 0x00020cUL
#define PHY_PCIE_REG_PHY0_K2 0x620000UL
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2 0x000210UL
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2 0x000214UL
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2 0x000208UL
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2 0x00020cUL
#define PHY_PCIE_REG_PHY1_K2 0x624000UL
#define PCIE_REG_DBG_REPEAT_THRESHOLD_COUNT_K2 0x054364UL
#define PCIE_REG_DBG_FW_TRIGGER_ENABLE_K2 0x05436cUL
#define RDIF_REG_DEBUG_ERROR_INFO 0x300400UL
#define RDIF_REG_DEBUG_ERROR_INFO_SIZE 64
#define RDIF_REG_DEBUG_ERROR_INFO_SIZE 64
#define TDIF_REG_DEBUG_ERROR_INFO 0x310400UL
#define TDIF_REG_DEBUG_ERROR_INFO_SIZE 64
#define TDIF_REG_DEBUG_ERROR_INFO_SIZE 64
#define SEM_FAST_REG_VFC_STATUS 0x000b4cUL
  #define SEM_FAST_REG_VFC_STATUS_RESPONSE_READY (0x1UL << 0)
  #define SEM_FAST_REG_VFC_STATUS_RESPONSE_READY_SHIFT 0
  #define SEM_FAST_REG_VFC_STATUS_VFC_BUSY (0x1UL << 1)
  #define SEM_FAST_REG_VFC_STATUS_VFC_BUSY_SHIFT 1
  #define SEM_FAST_REG_VFC_STATUS_SENDING_CMD_ON_GOING (0x1UL << 2)
  #define SEM_FAST_REG_VFC_STATUS_SENDING_CMD_ON_GOING_SHIFT 2
#define RSS_REG_RSS_RAM_DATA_SIZE 4
#define BRB_REG_BIG_RAM_DATA_SIZE 64
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1 0x0084c0UL
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO0 (0x1UL << 0)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO0_SHIFT 0
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO1 (0x1UL << 1)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO1_SHIFT 1
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO2 (0x1UL << 2)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO2_SHIFT 2
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO3 (0x1UL << 3)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO3_SHIFT 3
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO4 (0x1UL << 4)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO4_SHIFT 4
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO5 (0x1UL << 5)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO5_SHIFT 5
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO6 (0x1UL << 6)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO6_SHIFT 6
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO (0x1UL << 7)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO_SHIFT 7
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO8 (0x1UL << 8)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO8_SHIFT 8
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO9 (0x1UL << 9)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO9_SHIFT 9
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO10 (0x1UL << 10)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO10_SHIFT 10
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO11 (0x1UL << 11)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO11_SHIFT 11
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO12 (0x1UL << 12)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO12_SHIFT 12
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO13 (0x1UL << 13)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO13_SHIFT 13
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO14 (0x1UL << 14)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO14_SHIFT 14
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO15 (0x1UL << 15)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO15_SHIFT 15
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO16 (0x1UL << 16)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO16_SHIFT 16
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO17 (0x1UL << 17)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO17_SHIFT 17
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO18 (0x1UL << 18)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO18_SHIFT 18
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO19 (0x1UL << 19)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO19_SHIFT 19
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO20 (0x1UL << 20)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO20_SHIFT 20
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO21 (0x1UL << 21)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO21_SHIFT 21
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO22 (0x1UL << 22)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO22_SHIFT 22
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO23 (0x1UL << 23)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO23_SHIFT 23
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO24 (0x1UL << 24)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO24_SHIFT 24
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO25 (0x1UL << 25)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO25_SHIFT 25
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO26 (0x1UL << 26)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO26_SHIFT 26
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO27 (0x1UL << 27)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO27_SHIFT 27
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO28 (0x1UL << 28)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO28_SHIFT 28
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO29 (0x1UL << 29)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO29_SHIFT 29
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO30 (0x1UL << 30)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO30_SHIFT 30
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO31 (0x1UL << 31)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2 0x0084e4UL
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO0 (0x1UL << 0)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO0_SHIFT 0
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO1 (0x1UL << 1)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO1_SHIFT 1
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO2 (0x1UL << 2)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO2_SHIFT 2
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO3 (0x1UL << 3)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO3_SHIFT 3
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO4 (0x1UL << 4)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO4_SHIFT 4
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO5 (0x1UL << 5)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO5_SHIFT 5
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO6 (0x1UL << 6)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO6_SHIFT 6
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO (0x1UL << 7)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO_SHIFT 7
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO8 (0x1UL << 8)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO8_SHIFT 8
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO9 (0x1UL << 9)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO9_SHIFT 9
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO10 (0x1UL << 10)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO10_SHIFT 10
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO11 (0x1UL << 11)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO11_SHIFT 11
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO12 (0x1UL << 12)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO12_SHIFT 12
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO13 (0x1UL << 13)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO13_SHIFT 13
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO14 (0x1UL << 14)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO14_SHIFT 14
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO15 (0x1UL << 15)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO15_SHIFT 15
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO16 (0x1UL << 16)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO16_SHIFT 16
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO17 (0x1UL << 17)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO17_SHIFT 17
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO18 (0x1UL << 18)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO18_SHIFT 18
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO19 (0x1UL << 19)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO19_SHIFT 19
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO20 (0x1UL << 20)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO20_SHIFT 20
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO21 (0x1UL << 21)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO21_SHIFT 21
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO22 (0x1UL << 22)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO22_SHIFT 22
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO23 (0x1UL << 23)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO23_SHIFT 23
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO24 (0x1UL << 24)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO24_SHIFT 24
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO25 (0x1UL << 25)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO25_SHIFT 25
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO26 (0x1UL << 26)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO26_SHIFT 26
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO27 (0x1UL << 27)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO27_SHIFT 27
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO28 (0x1UL << 28)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO28_SHIFT 28
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO29 (0x1UL << 29)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO29_SHIFT 29
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO30 (0x1UL << 30)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO30_SHIFT 30
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO31 (0x1UL << 31)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3 0x008508UL
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO0 (0x1UL << 0)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO0_SHIFT 0
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO1 (0x1UL << 1)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO1_SHIFT 1
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO2 (0x1UL << 2)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO2_SHIFT 2
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO3 (0x1UL << 3)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO3_SHIFT 3
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO4 (0x1UL << 4)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO4_SHIFT 4
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO5 (0x1UL << 5)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO5_SHIFT 5
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO6 (0x1UL << 6)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO6_SHIFT 6
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO (0x1UL << 7)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO_SHIFT 7
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO8 (0x1UL << 8)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO8_SHIFT 8
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO9 (0x1UL << 9)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO9_SHIFT 9
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO10 (0x1UL << 10)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO10_SHIFT 10
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO11 (0x1UL << 11)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO11_SHIFT 11
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO12 (0x1UL << 12)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO12_SHIFT 12
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO13 (0x1UL << 13)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO13_SHIFT 13
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO14 (0x1UL << 14)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO14_SHIFT 14
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO15 (0x1UL << 15)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO15_SHIFT 15
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO16 (0x1UL << 16)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO16_SHIFT 16
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO17 (0x1UL << 17)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO17_SHIFT 17
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO18 (0x1UL << 18)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO18_SHIFT 18
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO19 (0x1UL << 19)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO19_SHIFT 19
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO20 (0x1UL << 20)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO20_SHIFT 20
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO21 (0x1UL << 21)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO21_SHIFT 21
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO22 (0x1UL << 22)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO22_SHIFT 22
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO23 (0x1UL << 23)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO23_SHIFT 23
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO24 (0x1UL << 24)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO24_SHIFT 24
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO25 (0x1UL << 25)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO25_SHIFT 25
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO26 (0x1UL << 26)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO26_SHIFT 26
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO27 (0x1UL << 27)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO27_SHIFT 27
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO28 (0x1UL << 28)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO28_SHIFT 28
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO29 (0x1UL << 29)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO29_SHIFT 29
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO30 (0x1UL << 30)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO30_SHIFT 30
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO31 (0x1UL << 31)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4 0x00852cUL
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO0 (0x1UL << 0)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO0_SHIFT 0
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO1 (0x1UL << 1)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO1_SHIFT 1
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO2 (0x1UL << 2)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO2_SHIFT 2
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO3 (0x1UL << 3)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO3_SHIFT 3
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO4 (0x1UL << 4)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO4_SHIFT 4
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO5 (0x1UL << 5)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO5_SHIFT 5
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO6 (0x1UL << 6)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO6_SHIFT 6
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO (0x1UL << 7)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO_SHIFT 7
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO8 (0x1UL << 8)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO8_SHIFT 8
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO9 (0x1UL << 9)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO9_SHIFT 9
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO10 (0x1UL << 10)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO10_SHIFT 10
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO11 (0x1UL << 11)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO11_SHIFT 11
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO12 (0x1UL << 12)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO12_SHIFT 12
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO13 (0x1UL << 13)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO13_SHIFT 13
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO14 (0x1UL << 14)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO14_SHIFT 14
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO15 (0x1UL << 15)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO15_SHIFT 15
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO16 (0x1UL << 16)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO16_SHIFT 16
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO17 (0x1UL << 17)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO17_SHIFT 17
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO18 (0x1UL << 18)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO18_SHIFT 18
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO19 (0x1UL << 19)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO19_SHIFT 19
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO20 (0x1UL << 20)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO20_SHIFT 20
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO21 (0x1UL << 21)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO21_SHIFT 21
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO22 (0x1UL << 22)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO22_SHIFT 22
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO23 (0x1UL << 23)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO23_SHIFT 23
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO24 (0x1UL << 24)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO24_SHIFT 24
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO25 (0x1UL << 25)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO25_SHIFT 25
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO26 (0x1UL << 26)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO26_SHIFT 26
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO27 (0x1UL << 27)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO27_SHIFT 27
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO28 (0x1UL << 28)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO28_SHIFT 28
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO29 (0x1UL << 29)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO29_SHIFT 29
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO30 (0x1UL << 30)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO30_SHIFT 30
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO31 (0x1UL << 31)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5 0x008550UL
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO0 (0x1UL << 0)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO0_SHIFT 0
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO1 (0x1UL << 1)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO1_SHIFT 1
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO2 (0x1UL << 2)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO2_SHIFT 2
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO3 (0x1UL << 3)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO3_SHIFT 3
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO4 (0x1UL << 4)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO4_SHIFT 4
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO5 (0x1UL << 5)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO5_SHIFT 5
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO6 (0x1UL << 6)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO6_SHIFT 6
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO (0x1UL << 7)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO_SHIFT 7
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO8 (0x1UL << 8)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO8_SHIFT 8
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO9 (0x1UL << 9)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO9_SHIFT 9
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO10 (0x1UL << 10)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO10_SHIFT 10
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO11 (0x1UL << 11)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO11_SHIFT 11
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO12 (0x1UL << 12)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO12_SHIFT 12
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO13 (0x1UL << 13)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO13_SHIFT 13
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO14 (0x1UL << 14)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO14_SHIFT 14
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO15 (0x1UL << 15)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO15_SHIFT 15
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO16 (0x1UL << 16)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO16_SHIFT 16
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO17 (0x1UL << 17)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO17_SHIFT 17
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO18 (0x1UL << 18)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO18_SHIFT 18
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO19 (0x1UL << 19)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO19_SHIFT 19
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO20 (0x1UL << 20)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO20_SHIFT 20
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO21 (0x1UL << 21)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO21_SHIFT 21
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO22 (0x1UL << 22)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO22_SHIFT 22
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO23 (0x1UL << 23)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO23_SHIFT 23
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO24 (0x1UL << 24)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO24_SHIFT 24
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO25 (0x1UL << 25)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO25_SHIFT 25
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO26 (0x1UL << 26)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO26_SHIFT 26
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO27 (0x1UL << 27)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO27_SHIFT 27
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO28 (0x1UL << 28)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO28_SHIFT 28
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO29 (0x1UL << 29)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO29_SHIFT 29
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO30 (0x1UL << 30)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO30_SHIFT 30
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO31 (0x1UL << 31)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6 0x008574UL
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO0 (0x1UL << 0)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO0_SHIFT 0
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO1 (0x1UL << 1)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO1_SHIFT 1
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO2 (0x1UL << 2)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO2_SHIFT 2
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO3 (0x1UL << 3)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO3_SHIFT 3
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO4 (0x1UL << 4)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO4_SHIFT 4
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO5 (0x1UL << 5)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO5_SHIFT 5
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO6 (0x1UL << 6)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO6_SHIFT 6
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO (0x1UL << 7)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO_SHIFT 7
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO8 (0x1UL << 8)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO8_SHIFT 8
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO9 (0x1UL << 9)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO9_SHIFT 9
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO10 (0x1UL << 10)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO10_SHIFT 10
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO11 (0x1UL << 11)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO11_SHIFT 11
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO12 (0x1UL << 12)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO12_SHIFT 12
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO13 (0x1UL << 13)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO13_SHIFT 13
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO14 (0x1UL << 14)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO14_SHIFT 14
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO15 (0x1UL << 15)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO15_SHIFT 15
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO16 (0x1UL << 16)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO16_SHIFT 16
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO17 (0x1UL << 17)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO17_SHIFT 17
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO18 (0x1UL << 18)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO18_SHIFT 18
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO19 (0x1UL << 19)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO19_SHIFT 19
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO20 (0x1UL << 20)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO20_SHIFT 20
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO21 (0x1UL << 21)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO21_SHIFT 21
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO22 (0x1UL << 22)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO22_SHIFT 22
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO23 (0x1UL << 23)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO23_SHIFT 23
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO24 (0x1UL << 24)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO24_SHIFT 24
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO25 (0x1UL << 25)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO25_SHIFT 25
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO26 (0x1UL << 26)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO26_SHIFT 26
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO27 (0x1UL << 27)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO27_SHIFT 27
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO28 (0x1UL << 28)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO28_SHIFT 28
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO29 (0x1UL << 29)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO29_SHIFT 29
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO30 (0x1UL << 30)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO30_SHIFT 30
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO31 (0x1UL << 31)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7 0x008598UL
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO0 (0x1UL << 0)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO0_SHIFT 0
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO1 (0x1UL << 1)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO1_SHIFT 1
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO2 (0x1UL << 2)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO2_SHIFT 2
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO3 (0x1UL << 3)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO3_SHIFT 3
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO4 (0x1UL << 4)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO4_SHIFT 4
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO5 (0x1UL << 5)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO5_SHIFT 5
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO6 (0x1UL << 6)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO6_SHIFT 6
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO (0x1UL << 7)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO_SHIFT 7
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO8 (0x1UL << 8)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO8_SHIFT 8
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO9 (0x1UL << 9)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO9_SHIFT 9
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO10 (0x1UL << 10)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO10_SHIFT 10
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO11 (0x1UL << 11)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO11_SHIFT 11
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO12 (0x1UL << 12)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO12_SHIFT 12
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO13 (0x1UL << 13)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO13_SHIFT 13
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO14 (0x1UL << 14)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO14_SHIFT 14
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO15 (0x1UL << 15)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO15_SHIFT 15
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO16 (0x1UL << 16)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO16_SHIFT 16
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO17 (0x1UL << 17)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO17_SHIFT 17
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO18 (0x1UL << 18)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO18_SHIFT 18
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO19 (0x1UL << 19)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO19_SHIFT 19
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO20 (0x1UL << 20)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO20_SHIFT 20
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO21 (0x1UL << 21)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO21_SHIFT 21
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO22 (0x1UL << 22)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO22_SHIFT 22
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO23 (0x1UL << 23)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO23_SHIFT 23
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO24 (0x1UL << 24)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO24_SHIFT 24
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO25 (0x1UL << 25)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO25_SHIFT 25
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO26 (0x1UL << 26)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO26_SHIFT 26
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO27 (0x1UL << 27)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO27_SHIFT 27
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO28 (0x1UL << 28)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO28_SHIFT 28
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO29 (0x1UL << 29)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO29_SHIFT 29
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO30 (0x1UL << 30)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO30_SHIFT 30
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO31 (0x1UL << 31)
  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_NIG 0x0085bcUL
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO0 (0x1UL << 0)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO0_SHIFT 0
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO1 (0x1UL << 1)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO1_SHIFT 1
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO2 (0x1UL << 2)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO2_SHIFT 2
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO3 (0x1UL << 3)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO3_SHIFT 3
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO4 (0x1UL << 4)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO4_SHIFT 4
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO5 (0x1UL << 5)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO5_SHIFT 5
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO6 (0x1UL << 6)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO6_SHIFT 6
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO (0x1UL << 7)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO_SHIFT 7
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO8 (0x1UL << 8)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO8_SHIFT 8
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO9 (0x1UL << 9)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO9_SHIFT 9
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO10 (0x1UL << 10)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO10_SHIFT 10
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO11 (0x1UL << 11)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO11_SHIFT 11
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO12 (0x1UL << 12)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO12_SHIFT 12
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO13 (0x1UL << 13)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO13_SHIFT 13
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO14 (0x1UL << 14)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO14_SHIFT 14
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO15 (0x1UL << 15)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO15_SHIFT 15
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO16 (0x1UL << 16)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO16_SHIFT 16
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO17 (0x1UL << 17)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO17_SHIFT 17
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO18 (0x1UL << 18)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO18_SHIFT 18
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO19 (0x1UL << 19)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO19_SHIFT 19
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO20 (0x1UL << 20)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO20_SHIFT 20
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO21 (0x1UL << 21)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO21_SHIFT 21
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO22 (0x1UL << 22)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO22_SHIFT 22
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO23 (0x1UL << 23)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO23_SHIFT 23
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO24 (0x1UL << 24)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO24_SHIFT 24
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO25 (0x1UL << 25)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO25_SHIFT 25
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO26 (0x1UL << 26)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO26_SHIFT 26
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO27 (0x1UL << 27)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO27_SHIFT 27
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO28 (0x1UL << 28)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO28_SHIFT 28
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO29 (0x1UL << 29)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO29_SHIFT 29
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO30 (0x1UL << 30)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO30_SHIFT 30
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO31 (0x1UL << 31)
  #define MISC_REG_AEU_ENABLE1_NIG_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_PXP 0x0085e0UL
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO0 (0x1UL << 0)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO0_SHIFT 0
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO1 (0x1UL << 1)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO1_SHIFT 1
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO2 (0x1UL << 2)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO2_SHIFT 2
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO3 (0x1UL << 3)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO3_SHIFT 3
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO4 (0x1UL << 4)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO4_SHIFT 4
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO5 (0x1UL << 5)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO5_SHIFT 5
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO6 (0x1UL << 6)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO6_SHIFT 6
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO (0x1UL << 7)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO_SHIFT 7
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO8 (0x1UL << 8)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO8_SHIFT 8
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO9 (0x1UL << 9)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO9_SHIFT 9
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO10 (0x1UL << 10)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO10_SHIFT 10
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO11 (0x1UL << 11)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO11_SHIFT 11
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO12 (0x1UL << 12)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO12_SHIFT 12
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO13 (0x1UL << 13)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO13_SHIFT 13
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO14 (0x1UL << 14)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO14_SHIFT 14
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO15 (0x1UL << 15)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO15_SHIFT 15
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO16 (0x1UL << 16)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO16_SHIFT 16
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO17 (0x1UL << 17)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO17_SHIFT 17
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO18 (0x1UL << 18)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO18_SHIFT 18
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO19 (0x1UL << 19)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO19_SHIFT 19
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO20 (0x1UL << 20)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO20_SHIFT 20
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO21 (0x1UL << 21)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO21_SHIFT 21
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO22 (0x1UL << 22)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO22_SHIFT 22
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO23 (0x1UL << 23)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO23_SHIFT 23
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO24 (0x1UL << 24)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO24_SHIFT 24
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO25 (0x1UL << 25)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO25_SHIFT 25
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO26 (0x1UL << 26)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO26_SHIFT 26
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO27 (0x1UL << 27)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO27_SHIFT 27
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO28 (0x1UL << 28)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO28_SHIFT 28
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO29 (0x1UL << 29)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO29_SHIFT 29
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO30 (0x1UL << 30)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO30_SHIFT 30
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO31 (0x1UL << 31)
  #define MISC_REG_AEU_ENABLE1_PXP_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0 0x008628UL
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO0 (0x1UL << 0)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO0_SHIFT 0
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO1 (0x1UL << 1)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO1_SHIFT 1
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO2 (0x1UL << 2)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO2_SHIFT 2
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO3 (0x1UL << 3)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO3_SHIFT 3
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO4 (0x1UL << 4)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO4_SHIFT 4
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO5 (0x1UL << 5)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO5_SHIFT 5
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO6 (0x1UL << 6)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO6_SHIFT 6
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO (0x1UL << 7)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO_SHIFT 7
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO8 (0x1UL << 8)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO8_SHIFT 8
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO9 (0x1UL << 9)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO9_SHIFT 9
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO10 (0x1UL << 10)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO10_SHIFT 10
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO11 (0x1UL << 11)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO11_SHIFT 11
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO12 (0x1UL << 12)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO12_SHIFT 12
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO13 (0x1UL << 13)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO13_SHIFT 13
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO14 (0x1UL << 14)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO14_SHIFT 14
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO15 (0x1UL << 15)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO15_SHIFT 15
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO16 (0x1UL << 16)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO16_SHIFT 16
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO17 (0x1UL << 17)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO17_SHIFT 17
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO18 (0x1UL << 18)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO18_SHIFT 18
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO19 (0x1UL << 19)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO19_SHIFT 19
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO20 (0x1UL << 20)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO20_SHIFT 20
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO21 (0x1UL << 21)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO21_SHIFT 21
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO22 (0x1UL << 22)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO22_SHIFT 22
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO23 (0x1UL << 23)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO23_SHIFT 23
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO24 (0x1UL << 24)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO24_SHIFT 24
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO25 (0x1UL << 25)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO25_SHIFT 25
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO26 (0x1UL << 26)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO26_SHIFT 26
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO27 (0x1UL << 27)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO27_SHIFT 27
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO28 (0x1UL << 28)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO28_SHIFT 28
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO29 (0x1UL << 29)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO29_SHIFT 29
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO30 (0x1UL << 30)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO30_SHIFT 30
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO31 (0x1UL << 31)
  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR 0x008748UL
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO0 (0x1UL << 0)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO0_SHIFT 0
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO1 (0x1UL << 1)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO1_SHIFT 1
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO2 (0x1UL << 2)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO2_SHIFT 2
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO3 (0x1UL << 3)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO3_SHIFT 3
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO4 (0x1UL << 4)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO4_SHIFT 4
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO5 (0x1UL << 5)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO5_SHIFT 5
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO6 (0x1UL << 6)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO6_SHIFT 6
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO (0x1UL << 7)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO_SHIFT 7
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO8 (0x1UL << 8)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO8_SHIFT 8
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO9 (0x1UL << 9)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO9_SHIFT 9
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO10 (0x1UL << 10)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO10_SHIFT 10
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO11 (0x1UL << 11)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO11_SHIFT 11
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO12 (0x1UL << 12)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO12_SHIFT 12
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO13 (0x1UL << 13)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO13_SHIFT 13
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO14 (0x1UL << 14)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO14_SHIFT 14
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO15 (0x1UL << 15)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO15_SHIFT 15
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO16 (0x1UL << 16)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO16_SHIFT 16
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO17 (0x1UL << 17)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO17_SHIFT 17
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO18 (0x1UL << 18)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO18_SHIFT 18
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO19 (0x1UL << 19)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO19_SHIFT 19
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO20 (0x1UL << 20)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO20_SHIFT 20
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO21 (0x1UL << 21)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO21_SHIFT 21
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO22 (0x1UL << 22)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO22_SHIFT 22
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO23 (0x1UL << 23)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO23_SHIFT 23
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO24 (0x1UL << 24)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO24_SHIFT 24
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO25 (0x1UL << 25)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO25_SHIFT 25
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO26 (0x1UL << 26)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO26_SHIFT 26
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO27 (0x1UL << 27)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO27_SHIFT 27
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO28 (0x1UL << 28)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO28_SHIFT 28
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO29 (0x1UL << 29)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO29_SHIFT 29
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO30 (0x1UL << 30)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO30_SHIFT 30
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO31 (0x1UL << 31)
  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_SYS_KILL 0x008604UL
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO0 (0x1UL << 0)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO0_SHIFT 0
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO1 (0x1UL << 1)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO1_SHIFT 1
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO2 (0x1UL << 2)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO2_SHIFT 2
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO3 (0x1UL << 3)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO3_SHIFT 3
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO4 (0x1UL << 4)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO4_SHIFT 4
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO5 (0x1UL << 5)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO5_SHIFT 5
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO6 (0x1UL << 6)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO6_SHIFT 6
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO (0x1UL << 7)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO_SHIFT 7
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO8 (0x1UL << 8)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO8_SHIFT 8
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO9 (0x1UL << 9)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO9_SHIFT 9
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO10 (0x1UL << 10)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO10_SHIFT 10
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO11 (0x1UL << 11)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO11_SHIFT 11
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO12 (0x1UL << 12)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO12_SHIFT 12
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO13 (0x1UL << 13)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO13_SHIFT 13
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO14 (0x1UL << 14)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO14_SHIFT 14
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO15 (0x1UL << 15)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO15_SHIFT 15
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO16 (0x1UL << 16)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO16_SHIFT 16
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO17 (0x1UL << 17)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO17_SHIFT 17
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO18 (0x1UL << 18)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO18_SHIFT 18
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO19 (0x1UL << 19)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO19_SHIFT 19
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO20 (0x1UL << 20)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO20_SHIFT 20
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO21 (0x1UL << 21)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO21_SHIFT 21
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO22 (0x1UL << 22)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO22_SHIFT 22
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO23 (0x1UL << 23)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO23_SHIFT 23
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO24 (0x1UL << 24)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO24_SHIFT 24
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO25 (0x1UL << 25)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO25_SHIFT 25
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO26 (0x1UL << 26)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO26_SHIFT 26
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO27 (0x1UL << 27)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO27_SHIFT 27
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO28 (0x1UL << 28)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO28_SHIFT 28
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO29 (0x1UL << 29)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO29_SHIFT 29
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO30 (0x1UL << 30)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO30_SHIFT 30
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO31 (0x1UL << 31)
  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO31_SHIFT 31
#define DBG_REG_FULL_BUFFER_THR 0x01045cUL
#define MISC_REG_AEU_MASK_ATTN_MCP 0x008498UL
#define MISC_REG_AEU_SYS_KILL_BEHAVIOR 0x008800UL
#define MISC_REG_AEU_GENERAL_MASK 0x008828UL
  #define MISC_REG_AEU_GENERAL_MASK_AEU_PXP_CLOSE_MASK (0x1UL << 0)
  #define MISC_REG_AEU_GENERAL_MASK_AEU_PXP_CLOSE_MASK_SHIFT 0
  #define MISC_REG_AEU_GENERAL_MASK_AEU_NIG_CLOSE_MASK (0x1UL << 1)
  #define MISC_REG_AEU_GENERAL_MASK_AEU_NIG_CLOSE_MASK_SHIFT 1
  #define MISC_REG_AEU_GENERAL_MASK_AEU_SYS_KILL_MASK (0x1UL << 2)
  #define MISC_REG_AEU_GENERAL_MASK_AEU_SYS_KILL_MASK_SHIFT 2
  #define MISC_REG_AEU_GENERAL_MASK_AEU_GLB_UNC_ERR_MASK (0x1UL << 3)
  #define MISC_REG_AEU_GENERAL_MASK_AEU_GLB_UNC_ERR_MASK_SHIFT 3
